sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLIT

Tree is inconsistent with the use of TCO register space offsets and
related preprocessor defines. The legacy space was offset from ACPI
PM base by 0x60, but this changed with later platforms. The convenient
way is to define the TCO registers relative to its base address and
subtract 0x60 here, but this change cannot be easily done tree-wide or
in one go.

For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until
all platforms use a clean style of tco_{read,write} accessor functions
instead of {read,write}_pmbase16(), or worse, inw/outl().

Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

7 files changed, 13 insertions, 0 deletions

diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index c2d24b29c6..5ecfe3eac1 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -34,6 +34,7 @@ config CPU_SPECIFIC_OPTIONS
 	select INTEL_GMA_SWSMISCI
 	select CPU_INTEL_COMMON
 	select CPU_HAS_L2_ENABLE_MSR
+	select TCO_SPACE_NOT_YET_SPLIT
 
 config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h
index dc8a7fadcd..1db5038673 100644
--- a/src/soc/intel/baytrail/include/soc/pm.h
+++ b/src/soc/intel/baytrail/include/soc/pm.h
@@ -222,6 +222,8 @@
 # define  UPRWC_WR_EN	 (1 << 1) /* USB Per-Port Registers Write Enable */
 #define GPE_CTRL		0x40
 #define PM2A_CNT_BLK		0x50
+
+#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
 #define TCO_RLD			0x60
 #define TCO_STS			0x64
 #	define SECOND_TO_STS	(1 << 17)
@@ -230,6 +232,7 @@
 #	define TCO_LOCK		(1 << 12)
 #	define TCO_TMR_HALT	(1 << 11)
 #define TCO_TMR			0x70
+#endif
 
 /* I/O ports */
 #define RST_CNT			0xcf9
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index f297b8f7a3..c35fa7473d 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
 	select NO_CBFS_MCACHE
+	select TCO_SPACE_NOT_YET_SPLIT
 
 config DCACHE_BSP_STACK_SIZE
 	hex
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h
index 6cb8d55873..131a996919 100644
--- a/src/soc/intel/braswell/include/soc/pm.h
+++ b/src/soc/intel/braswell/include/soc/pm.h
@@ -184,6 +184,8 @@
 # define  UPRWC_WR_EN	 (1 << 1) /* USB Per-Port Registers Write Enable */
 #define GPE_CTRL		0x40
 #define PM2A_CNT_BLK		0x50
+
+#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
 #define TCO_RLD			0x60
 #define TCO_STS			0x64
 #	define SECOND_TO_STS	(1 << 17)
@@ -192,6 +194,7 @@
 #	define TCO_LOCK		(1 << 12)
 #	define TCO_TMR_HALT	(1 << 11)
 #define TCO_TMR			0x70
+#endif
 
 #if !defined(__ASSEMBLER__) && !defined(__ACPI__)
 
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 5b73f4f941..3878f142a7 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -12,6 +12,7 @@ config SOC_SPECIFIC_OPTIONS
 	select INTEL_GMA_ACPI
 	select MRC_SETTINGS_PROTECT
 	select REG_SCRIPT
+	select TCO_SPACE_NOT_YET_SPLIT
 
 config BROADWELL_LPDDR3
 	bool
diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h
index 52fd364430..8bbc2de472 100644
--- a/src/soc/intel/broadwell/include/soc/pm.h
+++ b/src/soc/intel/broadwell/include/soc/pm.h
@@ -53,12 +53,15 @@
 #define  SWGPE_CTRL		(1 << 1)
 #define DEVACT_STS		0x44
 #define PM2_CNT			0x50
+
+#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
 #define TCO1_CNT		0x60
 #define  TCO_TMR_HLT		(1 << 11)
 #define TCO1_STS		0x64
 #define  DMISCI_STS		(1 << 9)
 #define TCO2_STS		0x66
 #define  TCO2_STS_SECOND_TO	(1 << 1)
+#endif
 
 #define GPE0_REG_MAX		4
 #define GPE0_REG_SIZE		32
diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig
index 4e187ff114..4800f3f804 100644
--- a/src/soc/intel/broadwell/pch/Kconfig
+++ b/src/soc/intel/broadwell/pch/Kconfig
@@ -23,6 +23,7 @@ config PCH_SPECIFIC_OPTIONS
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
 	select SPI_FLASH
+	select TCO_SPACE_NOT_YET_SPLIT
 
 config EHCI_BAR
 	hex