diff options
| author | Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> | 2022-04-21 16:40:06 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-06 01:43:26 +0000 |
| commit | e3178a16e0af1c89ab4816a0cd46421b20f7a470 (patch) | |
| tree | 1e71c9ef385d0eb132877fac8f8c3032dcb85830 /src/soc/intel | |
| parent | 7195cee17f0c2ac74806ae3a1005333c26f126e5 (diff) | |
common/intel/cse: Add function to perform CSE FW update in ramstage
When compressed ME RW blobs are used for CSE FW update, it has to be
loaded into memory to decompress. So perform CSE FW update in ramstage.
Alder Lake-N based nissa boards use compressed ME RW blobs to save on
SPI flash size. Enable CSE FW update in ramstage.
BRANCH=firmware-brya-14505.B
TEST=Perform CSE FW update on nivviks and verify upgrade/downgrade
works.
Change-Id: Ide9471146d186dca11fb020e5006eeaa01442669
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_lite.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index a3741ccc6a..d4f474d6f1 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <arch/cpu.h> +#include <bootstate.h> #include <console/console.h> #include <cbfs.h> #include <commonlib/region.h> @@ -11,6 +13,7 @@ #include <security/vboot/vboot_common.h> #include <security/vboot/misc.h> #include <soc/intel/common/reset.h> +#include <timestamp.h> #define BPDT_HEADER_SZ sizeof(struct bpdt_header) #define BPDT_ENTRY_SZ sizeof(struct bpdt_entry) @@ -1119,3 +1122,17 @@ void cse_fw_sync(void) cse_trigger_vboot_recovery(CSE_LITE_SKU_RW_SWITCH_ERROR); } } + +static void ramstage_cse_fw_sync(void *unused) +{ + bool s3wake; + s3wake = acpi_get_sleep_type() == ACPI_S3; + + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && !s3wake) { + timestamp_add_now(TS_CSE_FW_SYNC_START); + cse_fw_sync(); + timestamp_add_now(TS_CSE_FW_SYNC_END); + } +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, ramstage_cse_fw_sync, NULL); |