src: change coreboot to lowercase

The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.

Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

8 files changed, 8 insertions, 8 deletions

diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index bdba305081..1548c305eb 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -33,7 +33,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	LIDS,	8,      // 0x02 - LID State
 	PWRS,	8,      // 0x03 - AC Power State
 	DPTE,	8,      // 0x04 - Enable DPTF
-	CBMC,	32,     // 0x05 - 0x08 - Coreboot Memory Console
+	CBMC,	32,     // 0x05 - 0x08 - coreboot Memory Console
 	PM1I,	64,     // 0x09 - 0x10 - System Wake Source - PM1 Index
 	GPEI,	64,     // 0x11 - 0x18 - GPE Wake Source
 	NHLA,	64,     // 0x19 - 0x20 - NHLT Address
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index f9cc49d3ff..e0b223fa48 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -33,7 +33,7 @@ typedef struct global_nvs_t {
 	uint8_t		lids; /* 0x02 - LID State */
 	uint8_t		pwrs; /* 0x03 - AC Power State */
 	uint8_t		dpte; /* 0x04 - Enable DPTF */
-	uint32_t	cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */
+	uint32_t	cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
 	uint64_t	pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
 	uint64_t	gpei; /* 0x11 - 0x18 - GPE Wake Source */
 	uint64_t	nhla; /* 0x19 - 0x20 - NHLT Address */
diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl
index fcc80d4460..b3b3a4f0c0 100644
--- a/src/soc/intel/broadwell/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/acpi/globalnvs.asl
@@ -55,7 +55,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	LIDS,	8,	// 0x16 - LID State
 	PWRS,	8,	// 0x17 - AC Power State
 	CMEM,	32,	// 0x18 - 0x1b - CBMEM TOC
-	CBMC,	32,	// 0x1c - 0x1f - Coreboot Memory Console
+	CBMC,	32,	// 0x1c - 0x1f - coreboot Memory Console
 	PM1I,	64,	// 0x20 - 0x27 - PM1 wake status bit
 	GPEI,	64,	// 0x28 - 0x2f - GPE wake status bit
 
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 202c56ae2f..55d6c8b4ea 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -46,7 +46,7 @@ typedef struct {
 	u8	lids; /* 0x16 - LID State */
 	u8	pwrs; /* 0x17 - AC Power State */
 	u32	cmem; /* 0x18 - 0x1b - CBMEM TOC */
-	u32	cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */
+	u32	cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
 	u64	pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
 	u64	gpei; /* 0x28 - 0x2f - GPE wake status bit */
 	u8	unused[208];
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index ab3c63ca8f..d06269f2ae 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -57,7 +57,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	LIDS,	8,	// 0x16 - LID State
 	PWRS,	8,	// 0x17 - AC Power State
 	CMEM,	32,	// 0x18 - 0x1b - CBMEM TOC
-	CBMC,	32,	// 0x1c - 0x1f - Coreboot Memory Console
+	CBMC,	32,	// 0x1c - 0x1f - coreboot Memory Console
 	PM1I,	64,	// 0x20 - 0x27 - PM1 wake status bit
 	GPEI,	64,	// 0x28 - 0x2f - GPE wake status bit
 	DPTE,	8,	// 0x30 - Enable DPTF
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 61975c648c..ab069488a0 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -182,7 +182,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	 * To disable Heci, the Psf needs to be left unlocked
 	 * by FSP after end of post sequence. Based on the devicetree
 	 * setting, we set the appropriate PsfUnlock policy in Fsp,
-	 * do the changes and then lock it back in Coreboot
+	 * do the changes and then lock it back in coreboot
 	 *
 	 */
 	if (config->HeciEnabled == 0)
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 95d9ad9c8c..dddc1c3c7e 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -226,7 +226,7 @@ static void configure_isst(void)
 	if (conf->speed_shift_enable) {
 		/*
 		* Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
-		  is supported or not. Coreboot needs to configure MSR 0x1AA
+		  is supported or not. coreboot needs to configure MSR 0x1AA
 		  which is then reflected in the CPUID register.
 		*/
 		msr = rdmsr(MSR_MISC_PWR_MGMT);
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index cb3b2c6ee5..f72616f05e 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -47,7 +47,7 @@ typedef struct {
 	u8	lids; /* 0x16 - LID State */
 	u8	pwrs; /* 0x17 - AC Power State */
 	u32	cmem; /* 0x18 - 0x1b - CBMEM TOC */
-	u32	cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */
+	u32	cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
 	u64	pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
 	u64	gpei; /* 0x28 - 0x2f - GPE wake status bit */
 	u8	dpte; /* 0x30 - Enable DPTF */