diff options
| author | Andrey Petrov <anpetrov@fb.com> | 2019-12-30 09:58:47 -0800 |
|---|---|---|
| committer | Andrey Petrov <anpetrov@fb.com> | 2020-01-30 21:32:17 +0000 |
| commit | dafd514d306d226e7157ac633f97f7c50923814a (patch) | |
| tree | ae3b741e070163d80cf44d7cafe02e173427f4f4 /src/soc/intel | |
| parent | b729d8b6e3e3773a2d2b848a5008ad531a066504 (diff) | |
soc/intel/common/systemagent: Add Kconfig guard
Looks like selecting SOC_INTEL_COMMON force-sets MMCONF_BASE_ADDR to
some value which can't be overriden outside of soc/intel/common. So
adding a non-SoC platform thats uses code from soc/intel/common is not
possible.
TEST=build test on wip platform
Change-Id: Ia160444e8ac7cac55153f659f4d98f4f77f0d467
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/systemagent/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/Kconfig | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 1222573201..6dd1f3b363 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -3,6 +3,8 @@ config SOC_INTEL_COMMON_BLOCK_SA help Intel Processor common System Agent support +if SOC_INTEL_COMMON_BLOCK_SA + config MMCONF_BASE_ADDRESS hex default 0xe0000000 @@ -36,3 +38,5 @@ config SA_ENABLE_DPR default n help This option allows you to add the DMA Protected Range (DPR). + +endif diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index fa49eb0d9a..aed2beb3fd 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -54,6 +54,10 @@ config CPU_SPECIFIC_OPTIONS select UDK_2015_BINDING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + config FSP_T_ADDR hex "Intel FSP-T (temp ram init) binary location" depends on ADD_FSP_BINARIES && FSP_CAR |