diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-08-30 20:54:16 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-01 05:15:05 +0000 |
| commit | d37ebddfd84699464d076642f35fce0ef21cd1d5 (patch) | |
| tree | a102e4567a55a5194636201b2fd59b8ee1e5442d /src/soc/intel | |
| parent | c97b0607ff4883fc5ceab0da2c8687a91ece2d13 (diff) | |
soc/intel/canonlake: Enable LPSS UART in 32bit PCI mode
Cannonlake LPSS UART port can be working on both 32 bit and 8 bit mode.
To maintian compatibilty with previous generation of SOC, select 32 bit
mode as default.
Change-Id: Iaef8bceabc1b12e054ab4a364f98b568a9efcd85
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index df3cda1891..049b2bb0e5 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -60,7 +60,8 @@ config UART_DEBUG select CONSOLE_SERIAL select BOOTBLOCK_CONSOLE select DRIVERS_UART - select DRIVERS_UART_8250IO + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO config UART_FOR_CONSOLE int "Index for LPSS UART port to use for console" |