diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2021-06-09 19:27:06 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-10-26 15:29:47 +0000 |
| commit | cb2fd20c7f5cf43776dddfe2dbafeb19475e81f3 (patch) | |
| tree | 277bf2af3ac540589ba24be13203f7c0038bcaf1 /src/soc/intel | |
| parent | 9a7fbbc98e8610a0a5314470edd8d5dafe676a06 (diff) | |
soc/intel/common: Add HECI Reset flow in the CSE driver
This change is required as part of HECI Interface initialization in order
to put the host and CSE into a known good state for communication. Please
refer ME BIOS specification for more details. The change adds HECI
interface reset flow in the CSE driver. It enables coreboot to send HECI
commands before DRAM Init.
BUG=b:175516533
TEST=Run 50 cold reset cycles on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie078beaa33c6a35ae8f5f460d4354766aa710fba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index e41e337550..68a41e869c 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -111,6 +111,9 @@ void heci_init(uintptr_t tempbar) /* Enable Bus Master and MMIO Space */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + + /* Trigger HECI Reset and make Host ready for communication with CSE */ + heci_reset(); } static uint32_t read_bar(pci_devfn_t dev, uint32_t offset) |