summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorDamien Zammit <damien@zamaudio.com>2016-07-17 18:26:18 +1000
committerMartin Roth <martinroth@google.com>2016-07-19 18:55:50 +0200
commitb921725b52a98970af5786ca58d7e511fe8870dc (patch)
tree2da1eb86d9603ffc0595c5d3e7d4afe421c895f6 /src/soc/intel
parent47995fbb36d914d96b7c6e49d81135834dc3f157 (diff)
nb/intel/x4x: Fix CAS latency detection
Fix and use the failsafe CAS detection logic rather than recalulating the values from raw SPDs. Tested on GA-G41M-ES2L with 2x2GB DDR2-800 DIMMs (which worked before and still work) Change-Id: I6af0f1705d099f7bcbff8c9baa94a68dae689e01 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/15726 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions