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authorLee Leahy <leroy.p.leahy@intel.com>2017-01-04 08:26:53 -0800
committerMartin Roth <martinroth@google.com>2017-03-13 21:25:27 +0100
commitb8f532310719668ac3f13c4b02273bb256742163 (patch)
treee91016969612cad1b977cdf5eb9ec0e17da43cae /src/soc/intel
parentf59a75c99da593651217fda6f30f91ed45583ee8 (diff)
soc/intel/quark: Add the verstage files
Add the files to support verstage for vboot. TEST=Build and run on Galileo Gen2 Change-Id: Icf87075012c08cf581c17d579e0763888c707265 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18040 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/quark/Makefile.inc5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index bd297ed8d7..1d66e6beba 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -25,6 +25,11 @@ bootblock-y += reg_access.c
bootblock-y += tsc_freq.c
bootblock-y += uart_common.c
+verstage-y += i2c.c
+verstage-y += reg_access.c
+verstage-y += tsc_freq.c
+verstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
+
romstage-y += i2c.c
romstage-y += memmap.c
romstage-y += reg_access.c