soc/intel/quark: Add TempRamInit support

Successfully invoke TempRamInit from the FSP binary:
*  Don't relocate the FSP binary image
*  Copy the FSP binary into ESRAM
*  Specify Kconfig values to easily debug ESRAM and TempRamInit code
*  Specify the FSP binary file location
*  Specify the FSP binary image ID
*  Specify where in the flash image the FSP image must reside
*  Specify the FSP data file location
*  Specify where to place the FSP data file in the flash image
*  Specify where in the ESRAM the FSP image must reside

Test 1 on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
   *  Add "select ENABLE_DEBUG_LED_FINDFSP"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located,  The test fails if the SD LED is flashing.

Test 2 on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Remove "select ENABLE_DEBUG_LED_FINDFSP"
   *  Add "select ENABLE_DEBUG_LED_TEMPRAMINIT"
*  Testing is successful if the SD LED is on indicating that the FSP.bin
   file was properly located,  The test fails if the SD LED is flashing.

Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13443
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

5 files changed, 355 insertions, 0 deletions

diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 1bfab49c95..802f972058 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -29,6 +29,42 @@ config CPU_SPECIFIC_OPTIONS
 	select USE_MARCH_586
 
 #####
+# Debug support
+#     The following options provide debug support for the Quark coreboot
+#     code.  The SD LED is used as a binary marker to determine if a
+#     specific point in the execution flow has been reached.
+#####
+
+config ENABLE_DEBUG_LED
+	bool
+	default n
+	help
+	  Enable the use of the SD LED for early debugging before serial output
+	  is available.  Setting this LED indicates that control has reached the
+	  desired check point.
+
+config ENABLE_DEBUG_LED_ESRAM
+	bool "SD LED indicates ESRAM initialized"
+	default n
+	select ENABLE_DEBUG_LED
+	help
+	  Indicate that ESRAM has been successfully initialized.
+
+config ENABLE_DEBUG_LED_FINDFSP
+	bool "SD LED indicates fsp.bin file was found"
+	default n
+	select ENABLE_DEBUG_LED
+	help
+	  Indicate that fsp.bin was found.
+
+config ENABLE_DEBUG_LED_TEMPRAMINIT
+	bool "SD LED indicates TempRamInit was successful"
+	default n
+	select ENABLE_DEBUG_LED
+	help
+	  Indicate that TempRamInit was successful.
+
+#####
 # Flash layout
 #     Specify the size of the coreboot file system in the read-only
 #     (recovery) portion of the flash part.
@@ -45,6 +81,88 @@ config CBFS_SIZE
 	   - Intel Trusted Execution Engine firmware
 
 #####
+# FSP binary
+#     The following options control the FSP binary file placement in
+#     the flash image and ESRAM.  This file is required by the Quark
+#     SoC code to boot coreboot and its payload.
+#####
+
+config ADD_FSP_RAW_BIN
+	bool "Add the Intel FSP binary to the flash image without relocation"
+	default n
+	depends on PLATFORM_USES_FSP1_1
+	help
+	  Select this option to add an Intel FSP binary to
+	  the resulting coreboot image.
+
+	  Note: Without this binary, coreboot builds relying on the FSP
+	  will not boot
+
+config FSP_FILE
+	string "Intel FSP binary path and filename"
+	default "3rdparty/blobs/soc/intel/quark/fsp.bin"
+	depends on PLATFORM_USES_FSP1_1
+	depends on ADD_FSP_RAW_BIN
+	help
+	  The path and filename of the Intel FSP binary for this platform.
+
+config FSP_IMAGE_ID_STRING
+	string "8 byte platform string identifying the FSP platform"
+	default "QUK-FSP0"
+	depends on PLATFORM_USES_FSP1_1
+	help
+	  8 ASCII character byte signature string that will help match the FSP
+	  binary to a supported hardware configuration.
+
+config FSP_LOC
+	hex
+	default 0xfff80000
+	depends on PLATFORM_USES_FSP1_1
+	help
+	  The location in CBFS that the FSP is located. This must match the
+	  value that is set in the FSP binary.  If the FSP needs to be moved,
+	  rebase the FSP with Intel's BCT (tool).
+
+config FSP_ESRAM_LOC
+	hex
+	default 0x80000000
+	depends on PLATFORM_USES_FSP1_1
+	help
+	  The location in ESRAM where a copy of the FSP binary is placed.
+
+#####
+# FSP PDAT binary
+#     The following options control the FSP platform data binary
+#     file placement in the flash image.
+#####
+
+config ADD_FSP_PDAT_FILE
+	bool "Should the PDAT binary be added to the flash image?"
+	default n
+	depends on PLATFORM_USES_FSP1_1
+	help
+	  The PDAT file is required for the FSP 1.1 binary
+
+config FSP_PDAT_FILE
+	string
+	default "3rdparty/blobs/soc/intel/quark/pdat.bin"
+	depends on PLATFORM_USES_FSP1_1
+	depends on ADD_FSP_PDAT_FILE
+	help
+	  The path and filename of the Intel Galileo platform-data-patch (PDAT)
+	  binary. This binary file is generated by the platform-data-patch.py
+	  script released with the Quark BSP and contains the Ethernet address.
+
+config FSP_PDAT_LOC
+	hex
+	default 0xfff10000
+	depends on PLATFORM_USES_FSP1_1
+	depends on ADD_FSP_PDAT_FILE
+	help
+	  The location in CBFS that the PDAT is located. It must match the
+	  PCD PcdPlatformDataBaseAddress of Quark SoC FSP.
+
+#####
 # RMU binary
 #     The following options control the Quark chipset microcode file
 #     placement in the flash image.  This file is required to bring
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index 8e24d9b44f..880f1d484c 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -27,6 +27,18 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include
 # Chipset microcode path
 CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
 
+# Add the FSP binary to the CBFS image
+cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin
+fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
+fsp.bin-position := $(CONFIG_FSP_LOC)
+fsp.bin-type := raw
+
+# Add the platform data file to the CBFS image
+cbfs-files-$(CONFIG_ADD_FSP_PDAT_FILE) += pdat.bin
+pdat.bin-file := $(call strip_quotes,$(CONFIG_FSP_PDAT_FILE))
+pdat.bin-position := $(CONFIG_FSP_PDAT_LOC)
+pdat.bin-type := raw
+
 # Add the chipset microcode file to the CBFS image
 cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin
 rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE))
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index a0be5d5d11..cb17d3d155 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -14,3 +14,4 @@
 #
 
 cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
+cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc
new file mode 100644
index 0000000000..d323f03b51
--- /dev/null
+++ b/src/soc/intel/quark/romstage/cache_as_ram.inc
@@ -0,0 +1,206 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Replacement for cache_as_ram.inc when using the FSP binary.  This code
+ * locates the FSP binary, initializes the cache as RAM and performs the
+ * first stage of initialization.  Next this code switches the stack from
+ * the cache to RAM and then disables the cache as RAM.  Finally this code
+ * performs the final stage of initialization.
+ */
+
+#include <rules.h>
+
+	/*
+	 * eax:  BIST value
+	 */
+
+	movl	%eax, %edi
+
+cache_as_ram:
+	post_code(0x20)
+
+	/*
+	 * edi:  BIST value
+	 */
+
+	/*
+	 * Find the FSP binary in cbfs.
+	 * Make a fake stack that has the return value back to this code.
+	 */
+	lea	fake_fsp_stack, %esp
+	jmp	find_fsp
+
+find_fsp_ret:
+	/* Save the FSP location */
+	mov	%eax, %ebp
+
+	/*
+	 * Only when a valid FSP binary is found at CONFIG_FSP_LOC is
+	 * the returned FSP_INFO_HEADER structure address above the base
+	 * address of FSP binary specified by the CONFIG_FSP_LOC value.
+	 * All of the error values are in the 0x8xxxxxxx range which are
+	 * below the CONFIG_FSP_LOC value.
+	 */
+	cmp	$CONFIG_FSP_ESRAM_LOC, %eax
+	jbe	halt1
+
+	post_code(POST_FSP_TEMP_RAM_INIT)
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
+	movl	$SD_HOST_CTRL, %ebx
+	movb	0(%ebx), %al
+	orb	$1, %al
+	movb	%al, 0(%ebx)
+	jmp	.
+#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
+
+	/* Calculate entry into FSP */
+	mov	0x30(%ebp), %eax	/* Load TempRamInitEntry */
+	add	0x1c(%ebp), %eax	/* add in the offset for FSP */
+
+	/*
+	 * Pass early init variables on a fake stack (no memory yet)
+	 * as well as the return location
+	 */
+	lea	CAR_init_stack, %esp
+
+	/*
+	 *       BIST value is zero
+	 * eax:  TempRamInitApi address
+	 * ebp:  FSP_INFO_HEADER address
+	 * edi:  BIST value
+	 * esi:  Not used
+	 */
+
+	/* call FSP binary to setup temporary stack */
+	jmp	*%eax
+
+CAR_init_done:
+	addl	$4, %esp
+
+	/*
+	 * ebp:  FSP_INFO_HEADER address
+	 * ecx:  Temp RAM base
+	 * edx:  Temp RAM top
+	 * edi:  BIST value
+	 */
+
+	cmp	$0, %eax
+	jne	halt2
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT)
+	movl	%edx, %esi
+	movl	$SD_HOST_CTRL, %ebx
+	movb	0(%ebx), %al
+	orb	$1, %al
+	movb	%al, 0(%ebx)
+	movl	%esi, %edx
+	jmp	.
+#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */
+
+	/* Set up bootloader stack */
+	clrl	%eax
+	jmp	.Lhlt
+
+halt1:
+	/*
+	 * Failures for postcode 0xBA - failed in fsp_fih_early_find()
+	 *
+	 * Values are:
+	 * 0x01 - FV signature, "_FVH" not present
+	 * 0x02 - FFS GUID not present
+	 * 0x03 - FSP INFO Header not found
+	 * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
+	 *        a different location, or does it need to be?
+	 * 0x05 - FSP INFO Header signature "FSPH" not found
+	 * 0x06 - FSP Image ID is not the expected ID.
+	 */
+	movb	$0xBA, %ah
+	jmp	.Lhlt
+
+halt2:
+	/*
+	 * Failures for postcode 0xBB - failed in the FSP:
+	 *
+	 * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.
+	 * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
+	 * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
+	 * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
+	 * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
+	 * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
+	 */
+	movb	$0xBB, %ah
+	jmp	.Lhlt
+
+#----------------------------------------------------------------------------
+#
+# Procedure:	.Lhlt
+#
+# Input:	ah - Upper 8-bits of POST code
+#		al - Lower 8-bits of POST code
+#
+# Description:
+#		Infinite loop displaying alternating POST code values
+#
+#----------------------------------------------------------------------------
+
+#define FLASH_DELAY	0x1000	/* I/O delay between post codes on failure */
+#define POST_DELAY	0x50
+
+.Lhlt:
+	xchg	%al, %ah
+	mov	$POST_DELAY, %dh
+#if IS_ENABLED(CONFIG_POST_IO)
+	outb	%al, $CONFIG_POST_IO_PORT
+#else
+	post_code(POST_DEAD_CODE)
+#endif
+.flash_setup:
+	movl	$FLASH_DELAY, %ecx
+.flash_delay:
+	outb	%al, $0xED
+	loop	.flash_delay
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
+	movl	$SD_HOST_CTRL, %ebx
+	movb	0(%ebx), %dl
+	xorb	$1, %dl
+	movb	%dl, 0(%ebx)
+#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
+	decb	%dh
+	jnz	.flash_setup
+	jmp	.Lhlt
+
+/*
+ * esp is set to this location so that the call into and return from the FSP
+ * in find_fsp will work.
+ */
+	.align 4
+fake_fsp_stack:
+	.long	find_fsp_ret
+	.long	CONFIG_FSP_ESRAM_LOC	/* FSP base address */
+
+CAR_init_params:
+	.long	CONFIG_CPU_MICROCODE_CBFS_LOC		/* Microcode Location */
+	.long	CONFIG_CPU_MICROCODE_CBFS_LEN		/* Microcode Length */
+	.long	0xFFFFFFFF - CONFIG_ROM_SIZE + 1	/* Firmware Location */
+	.long	CONFIG_ROM_SIZE				/* Total Firmware Length */
+
+CAR_init_stack:
+	.long	CAR_init_done
+	.long	CAR_init_params
diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc
index 1b83c13633..b8997415f9 100644
--- a/src/soc/intel/quark/romstage/esram_init.inc
+++ b/src/soc/intel/quark/romstage/esram_init.inc
@@ -452,6 +452,21 @@ stackless_PCIConfig_Read:
 
 esram_init_done:
 
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
+
+	/* Copy FSP image to eSRAM and call it. */
+	/* TODO: FSP location/size could be got in a routine. */
+	cld
+	movl	$(0x00040000), %ecx               /* 256K DWORDs = 64K */
+	shrl	$2, %ecx
+	movl	$CONFIG_FSP_LOC, %esi   /* The source address. */
+	movl	$CONFIG_FSP_ESRAM_LOC, %edi   /* FSP destination in ESRAM */
+	rep	movsl
+#endif /* CONFIG_PLATFORM_USES_FSP1_1 */
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED)
+sd_led:
+
 .equ  SD_PFA, (0x14 << 11)    		/* B0:D20:F0 - SDIO controller */
 .equ  SD_CFG_BASE, (PCI_CFG | SD_PFA)	/* SD cntrl base in PCI config space */
 .equ  SD_CFG_CMD, (SD_CFG_BASE+0x04)	/* Command reg in PCI config space */
@@ -488,6 +503,7 @@ L43:
 	jmp	stackless_PCIConfig_Read
 
 L44:
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM)
 	/* Turn on SD LED to indicate ESRAM successfully initialized */
 	movl	$SD_HOST_CTRL, %ebx
 	movb	0(%ebx), %al
@@ -496,3 +512,5 @@ L44:
 
 	/* Loop forever */
 	jmp	.
+#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */
+#endif /* CONFIG_ENABLE_DEBUG_LED */