soc/intel/apollolake: Switch to common p2sb

Using common p2sb driver instead of private one.

TEST=Boot up into OS, and read back registers through PCR by iotools,
return is not 0xffffffff.

Change-Id: I30f3ef7bc37a8cb268af6fe2e4da3ec835c17633
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

5 files changed, 2 insertions, 104 deletions

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 36981efdbc..e8bfb07187 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -75,6 +75,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_LPC
 	select SOC_INTEL_COMMON_BLOCK_LPSS
 	select SOC_INTEL_COMMON_BLOCK_PCR
+	select SOC_INTEL_COMMON_BLOCK_P2SB
 	select SOC_INTEL_COMMON_BLOCK_PMC
 	select SOC_INTEL_COMMON_BLOCK_RTC
 	select SOC_INTEL_COMMON_BLOCK_SA
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index e860daa5ce..2848beddbe 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -56,7 +56,6 @@ ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 ramstage-y += lpc.c
 ramstage-y += memmap.c
 ramstage-y += mmap_boot.c
-ramstage-y += p2sb.c
 ramstage-y += uart.c
 ramstage-y += nhlt.c
 ramstage-y += systemagent.c
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 405a45c8e2..74e21907f0 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -28,6 +28,7 @@
 #include <device/pci.h>
 #include <intelblocks/acpi.h>
 #include <intelblocks/fast_spi.h>
+#include <intelblocks/p2sb.h>
 #include <intelblocks/msr.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
@@ -43,7 +44,6 @@
 #include <spi-generic.h>
 #include <soc/cpu.h>
 #include <soc/pm.h>
-#include <soc/p2sb.h>
 #include <soc/systemagent.h>
 
 #include "chip.h"
diff --git a/src/soc/intel/apollolake/include/soc/p2sb.h b/src/soc/intel/apollolake/include/soc/p2sb.h
deleted file mode 100644
index a0bcc67f45..0000000000
--- a/src/soc/intel/apollolake/include/soc/p2sb.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_APOLLOLAKE_P2SB_H_
-#define _SOC_APOLLOLAKE_P2SB_H_
-
-void p2sb_unhide(void);
-void p2sb_hide(void);
-
-#endif /* _SOC_APOLLOLAKE_P2SB_H_ */
diff --git a/src/soc/intel/apollolake/p2sb.c b/src/soc/intel/apollolake/p2sb.c
deleted file mode 100644
index f0e584b27f..0000000000
--- a/src/soc/intel/apollolake/p2sb.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <rules.h>
-#include <soc/iomap.h>
-#include <soc/pci_devs.h>
-#include <soc/p2sb.h>
-
-#define P2SB_E0 0xe0
-#define HIDE_BIT (1 << 0)
-
-static void p2sb_set_hide_bit(int hide)
-{
-	struct device *dev;
-	const uint16_t reg = P2SB_E0 + 1;
-	const uint8_t mask = HIDE_BIT;
-	uint8_t val;
-
-	dev = PCH_DEV_P2SB;
-
-	val = pci_read_config8(dev, reg);
-	val &= ~mask;
-	if (hide)
-		val |= mask;
-	pci_write_config8(dev, reg, val);
-}
-
-void p2sb_unhide(void)
-{
-	p2sb_set_hide_bit(0);
-}
-
-void p2sb_hide(void)
-{
-	p2sb_set_hide_bit(HIDE_BIT);
-}
-
-static void read_resources(struct device *dev)
-{
-	/*
-	 * There's only one resource on the P2SB device. It's also already
-	 * manually set to a fixed address in earlier boot stages.
-	 */
-	mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB);
-}
-
-static const struct device_operations device_ops = {
-	.read_resources		= read_resources,
-	.set_resources		= DEVICE_NOOP,
-};
-
-static const unsigned short pci_device_ids[] = {
-	PCI_DEVICE_ID_INTEL_APL_P2SB,
-	PCI_DEVICE_ID_INTEL_GLK_P2SB,
-	0,
-};
-
-static const struct pci_driver pmc __pci_driver = {
-	.ops	= &device_ops,
-	.vendor	= PCI_VENDOR_ID_INTEL,
-	.devices = pci_device_ids,
-};