diff options
| author | zhaojohn <john.zhao@intel.com> | 2022-09-12 14:24:59 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-09-21 15:33:13 +0000 |
| commit | 88a496a9c81ba6447a4c1453a45d09ee79f30309 (patch) | |
| tree | 60c01a7f6d447af699cc618d2fbe8f9e42f9d373 /src/soc/intel | |
| parent | a0e36d8cbaad6ead0102721fdedb3b4c50f0273c (diff) | |
soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence
This patch provides a workaround which skips requesting IOM for D3 cold
entry sequence.
BUG=b:244082753
TEST=Verified MUX configuration after hot plugging Type-C devices on
Rex and MTL RVP boards.
Change-Id: I17bcde75360c4b2b40885d355702e3e5f45d770a
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/meteorlake/acpi/tcss.asl | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl index 87d6521270..c2212f0f40 100644 --- a/src/soc/intel/meteorlake/acpi/tcss.asl +++ b/src/soc/intel/meteorlake/acpi/tcss.asl @@ -719,7 +719,13 @@ Scope (\_SB.PCI0) } /* Request IOM for D3 cold entry sequence. */ - TD3C = 1 + /* + * FIXME: Remove this workaround after resolving b/244082753 + * + * Document #742990: TCCold exit flow may not complete when processor at package + * C0. The implication is that the system may hang. + */ + // TD3C = 1 } PowerResource (D3C, 5, 0) |