diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2024-05-08 13:18:36 -0600 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-05-09 08:33:24 +0000 |
| commit | 817c58c2aeab0fabe912b58dbe4f24a81d6385ce (patch) | |
| tree | 784ad965894b1604c18bd7365e041fde3eab9d00 /src/soc/intel | |
| parent | 7e3cabec513e9dddfcd723b5c2adddeb1efdabaf (diff) | |
mb/google/brox: Sending End of Post (EOP) asynchronously
Currently EOP message is sent to CSE late in the boot flow. Instead send
it asynchronously to save ~10 ms in boot time.
BUG=b:337330958
TEST=Build Brox BIOS Image and boot to OS.
Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b124b140b8..e0afe5aeb7 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -82,7 +82,7 @@ config SOC_INTEL_ALDERLAKE select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET - select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON + select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON && !BOARD_GOOGLE_BROX_COMMON select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_GFX_MBUS_JOIN if MAINBOARD_HAS_CHROMEOS && BMP_LOGO select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION |