diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2022-01-09 02:17:30 +0100 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-01-14 00:29:13 +0000 |
| commit | 7a2bc06b121a978b7517230f7b8de2b5cc94c7e7 (patch) | |
| tree | 269e899bcced797c701d72ede48ec970e9eca66f /src/soc/intel | |
| parent | c14ba95bebf44154d512abd4741b080b5ed72fd8 (diff) | |
soc/intel/tgl/pcie_rp: add TGL-H support
Add TGL-H support for the recently introduced code for differentiating
CPU and PCH root ports by adding the missing TGL-H port map.
Change-Id: Id2911cddeb97d6c164662e2bef4fdeece10332a8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pcie_rp.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/pcie_rp.c | 19 |
2 files changed, 21 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index f5ed8927c9..b43987d13c 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -111,6 +111,9 @@ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups); */ uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups); +/* Get PCH root port groups */ +const struct pcie_rp_group *soc_get_pch_rp_groups(void); + enum pcie_rp_type { PCIE_RP_UNKNOWN, PCIE_RP_CPU, diff --git a/src/soc/intel/tigerlake/pcie_rp.c b/src/soc/intel/tigerlake/pcie_rp.c index 5966af6c2b..f45a9c4e96 100644 --- a/src/soc/intel/tigerlake/pcie_rp.c +++ b/src/soc/intel/tigerlake/pcie_rp.c @@ -12,6 +12,13 @@ static const struct pcie_rp_group pch_lp_rp_groups[] = { { 0 } }; +static const struct pcie_rp_group pch_h_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, + { 0 } +}; + static const struct pcie_rp_group cpu_rp_groups[] = { { .slot = SA_DEV_SLOT_PEG, .start = 0, .count = 3 }, { .slot = SA_DEV_SLOT_CPU_PCIE, .start = 0, .count = 1 }, @@ -40,9 +47,19 @@ static bool is_part_of_group(const struct device *dev, return false; } +const struct pcie_rp_group *soc_get_pch_rp_groups(void) +{ + if (CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)) + return pch_h_rp_groups; + else + return pch_lp_rp_groups; +} + enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) { - if (is_part_of_group(dev, pch_lp_rp_groups)) + const struct pcie_rp_group *pch_rp_groups = soc_get_pch_rp_groups(); + + if (is_part_of_group(dev, pch_rp_groups)) return PCIE_RP_PCH; if (is_part_of_group(dev, cpu_rp_groups)) |