soc/intel/cannonlake: Configure GPIO PM configuration in bootblock

This patch performs below operations:
1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration
2. Move soc_gpio_pm_configuration() to gpio_common.c
3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration
is updated with devicetree.cb value even with platform reset.

BUG=b:144002424
TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb

Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

5 files changed, 53 insertions, 17 deletions

diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 0fcbcd15e6..c744e9953d 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -89,6 +89,9 @@ smm-y += gpio.c
 verstage-y += gpio.c
 endif
 
+bootblock-y += gpio_common.c
+ramstage-y += gpio_common.c
+
 ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)
 # Not yet in intel-microcode repo
 #cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-66-*)
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 39433a26d9..9ad7e86178 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -28,6 +28,7 @@
 #include <intelblocks/smbus.h>
 #include <intelblocks/tco.h>
 #include <soc/bootblock.h>
+#include <soc/gpio.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
 #include <soc/p2sb.h>
@@ -198,4 +199,7 @@ void pch_early_init(void)
 	pmc_gpe_init();
 
 	enable_rtc_upper_bank();
+
+	/* GPIO community PM configuration */
+	soc_gpio_pm_configuration();
 }
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 0ce2f1aca7..2bb1c92612 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -23,6 +23,7 @@
 #include <intelblocks/xdci.h>
 #include <romstage_handoff.h>
 #include <soc/intel/common/vbt.h>
+#include <soc/gpio.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 
@@ -166,22 +167,6 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads)
 	gpio_configure_pads(cfg, num_pads);
 }
 
-/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */
-static void soc_fill_gpio_pm_configuration(void)
-{
-	uint8_t value[TOTAL_GPIO_COMM];
-	const config_t *config = config_of_soc();
-
-	if (config->gpio_override_pm)
-		memcpy(value, config->gpio_pm, sizeof(uint8_t) *
-			TOTAL_GPIO_COMM);
-	else
-		memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
-			TOTAL_GPIO_COMM);
-
-	gpio_pm_configure(value, TOTAL_GPIO_COMM);
-}
-
 void soc_init_pre_device(void *chip_info)
 {
 	/* Perform silicon specific init. */
@@ -193,7 +178,7 @@ void soc_init_pre_device(void *chip_info)
 	/* TODO(furquan): Get rid of this workaround once FSP is fixed. */
 	cnl_configure_pads(NULL, 0);
 
-	soc_fill_gpio_pm_configuration();
+	soc_gpio_pm_configuration();
 }
 
 static void pci_domain_set_resources(struct device *dev)
diff --git a/src/soc/intel/cannonlake/gpio_common.c b/src/soc/intel/cannonlake/gpio_common.c
new file mode 100644
index 0000000000..360189a0fd
--- /dev/null
+++ b/src/soc/intel/cannonlake/gpio_common.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/gpio.h>
+#include <soc/soc_chip.h>
+
+/*
+ * Routine to perform below operations:
+ * 1. SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register
+ * 2. Program GPIO PM configuration based on PM mask and value
+ */
+void soc_gpio_pm_configuration(void)
+{
+	uint8_t value[TOTAL_GPIO_COMM];
+	const config_t *config = config_of_soc();
+
+	if (config->gpio_override_pm)
+		memcpy(value, config->gpio_pm, sizeof(uint8_t) *
+				TOTAL_GPIO_COMM);
+	else
+		memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+				TOTAL_GPIO_COMM);
+
+	gpio_pm_configure(value, TOTAL_GPIO_COMM);
+}
diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h
index e7056ebcec..efed88180c 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio.h
@@ -28,6 +28,12 @@
 #ifndef __ACPI__
 struct pad_config;
 void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads);
+/*
+ * Routine to perform below operations:
+ * 1. SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register
+ * 2. Program GPIO PM configuration based on PM mask and value
+ */
+void soc_gpio_pm_configuration(void);
 #endif
 
 #endif