diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-04-18 13:31:57 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-27 12:35:10 +0000 |
| commit | 71fd0fa78008151286ce7b341f31b5cec0ff6553 (patch) | |
| tree | 0f6cfab3b5b7cdfc5ae638bd586742db4ef45c57 /src/soc/intel | |
| parent | bae4a0b5a1e413a8cf0bdce9be51ca006a02758a (diff) | |
soc/intel/alderlake: Implement PCH lock down configuration
This patch implements a function to enable IOSF Primary Trunk Clock
Gating.
BUG=b:211954778
TEST=Able to build and boot google/redrix to OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/lockdown.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c index 4b260da1af..d926dbbe2d 100644 --- a/src/soc/intel/alderlake/lockdown.c +++ b/src/soc/intel/alderlake/lockdown.c @@ -8,10 +8,16 @@ #include <device/mmio.h> #include <intelblocks/cfg.h> +#include <intelblocks/pcr.h> #include <intelpch/lockdown.h> +#include <soc/pcr_ids.h> #include <soc/pm.h> #include <stdint.h> +/* PCR PSTH Control Register */ +#define PCR_PSTH_CTRLREG 0x1d00 +#define PSTH_CTRLREG_IOSFPTCGE (1 << 2) + static void pmc_lockdown_cfg(int chipset_lockdown) { uint8_t *pmcbase = pmc_mmio_regs(); @@ -32,8 +38,19 @@ static void pmc_lockdown_cfg(int chipset_lockdown) } } +static void pch_lockdown_cfg(void) +{ + if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) + return; + + /* Enable IOSF Primary Trunk Clock Gating */ + pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE); +} + void soc_lockdown_config(int chipset_lockdown) { /* PMC lock down configuration */ pmc_lockdown_cfg(chipset_lockdown); + /* PCH lock down configuration */ + pch_lockdown_cfg(); } |