diff options
| author | Kane Chen <kane.chen@intel.corp-partner.google.com> | 2023-10-20 22:09:57 +0800 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-10-28 20:56:53 +0000 |
| commit | 6feb1de20a85686447ee7803935e85d7678c3d15 (patch) | |
| tree | ff12c9d06e257f1e637f8e25c92e4aaeab0c88f8 /src/soc/intel | |
| parent | d4bf7211ca72a6fe579f2d4bfadd64a6b3ef3f2d (diff) | |
soc/intel/meteoerlake: Add power limits for 2+4 15W SOC SKU
This commit adds power limit settings for 2+4 15w SOC sku and renames
MTL_P_282_CORE to MTL_P_282_242_CORE since they are sharing same 15w
settings.
BUG=b:306543967
TEST=boot on rex with 2+4 SOC and power limit settings are correct
Change-Id: Id738303d1652f964142f8f27110426d6b84609bf
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78495
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/meteorlake/chip.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/chipset.cb | 2 |
2 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 1e75019eab..818cc05a44 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -23,7 +23,7 @@ /* Types of different SKUs */ enum soc_intel_meteorlake_power_limits { - MTL_P_282_CORE, + MTL_P_282_242_CORE, MTL_P_682_CORE, MTL_POWER_LIMITS_COUNT }; @@ -40,7 +40,8 @@ static const struct { enum soc_intel_meteorlake_power_limits limits; enum soc_intel_meteorlake_cpu_tdps cpu_tdp; } cpuid_to_mtl[] = { - { PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_CORE, TDP_15W }, + { PCI_DID_INTEL_MTL_P_ID_5, MTL_P_282_242_CORE, TDP_15W }, + { PCI_DID_INTEL_MTL_P_ID_2, MTL_P_282_242_CORE, TDP_15W }, { PCI_DID_INTEL_MTL_P_ID_1, MTL_P_682_CORE, TDP_28W }, }; diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index ce4fe08850..4a49f22b1d 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -2,7 +2,7 @@ chip soc/intel/meteorlake device cpu_cluster 0 on end - register "power_limits_config[MTL_P_282_CORE]" = "{ + register "power_limits_config[MTL_P_282_242_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 57, .tdp_pl4 = 114, |