diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2017-05-05 15:44:20 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-05-08 06:10:25 +0200 |
| commit | 5c48b7e9f2d0249b07a673b4531a4781dd088616 (patch) | |
| tree | 9ff2e6a81fe8a88eb9b5892bc0e63c00a11f0179 /src/soc/intel | |
| parent | d06e06c36feef6494694d34800fa0706f6c4ff11 (diff) | |
soc/intel/skylake: remove unused SMI functions
The southbridge_trigger_smi() and southbridge_clear_smi_status()
functions are unused. Remove them.
Change-Id: I86994191a63cbf515bc330433ef7c3f79a39936e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/smm.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/skylake/smi.c | 32 |
2 files changed, 0 insertions, 38 deletions
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h index 71083b3cbf..6ba6fdb72c 100644 --- a/src/soc/intel/skylake/include/soc/smm.h +++ b/src/soc/intel/skylake/include/soc/smm.h @@ -61,10 +61,6 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, void smm_initialize(void); void smm_relocate(void); -/* These helpers are for performing SMM relocation. */ -void southbridge_trigger_smi(void); -void southbridge_clear_smi_status(void); - /* * The initialization of the southbridge is split into 2 compoments. One is * for clearing the state in the SMM registers. The other is for enabling @@ -80,8 +76,6 @@ static inline void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, static inline void smm_initialize(void) {} static inline void smm_relocate(void) {} -static inline void southbridge_trigger_smi(void) {} -static inline void southbridge_clear_smi_status(void) {} static inline void southbridge_smm_clear_state(void) {} static inline void southbridge_smm_enable_smi(void) {} #endif /* CONFIG_HAVE_SMI_HANDLER */ diff --git a/src/soc/intel/skylake/smi.c b/src/soc/intel/skylake/smi.c index 442607f2e7..734363713e 100644 --- a/src/soc/intel/skylake/smi.c +++ b/src/soc/intel/skylake/smi.c @@ -70,38 +70,6 @@ void southbridge_smm_enable_smi(void) enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS); } -void southbridge_trigger_smi(void) -{ - /* - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local apic is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - outb(0x00, 0xb2); -} - -void southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - clear_smi_status(); - - /* Clear PM1 status */ - clear_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - enable_smi(EOS); -} - void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { /* |