diff options
| author | Felix Singer <felixsinger@posteo.net> | 2020-07-29 22:28:37 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-08-08 12:01:18 +0000 |
| commit | 4d5c4e069cb99e715d04bf238e406a008f16707d (patch) | |
| tree | 5614365c7b55999717ea40ff9c0de809830915d0 /src/soc/intel | |
| parent | 88264ef30bcb20e8dd56de22cf564ebadd0bc2e9 (diff) | |
soc/intel/skylake: Enable SA IMGU depending on devicetree configuration
Currently, SA IMGU gets enabled by the option SaImguEnable,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SA IMGU controller.
All corresponding mainboards were checked if the devicetree
configuration matches the SaImguEnable setting, and missing entries
were added.
Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 1 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index cb0d2fc4ac..80e89f6cce 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -230,7 +230,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SerialIoDevMode)); params->PchCio2Enable = config->Cio2Enable; - params->SaImguEnable = config->SaImguEnable; + + dev = pcidev_path_on_root(SA_DEVFN_IMGU); + params->SaImguEnable = dev && dev->enabled; dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); params->Heci3Enabled = dev ? dev->enabled : 0; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 404a9f417e..33fe52c2b6 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -302,7 +302,6 @@ struct soc_intel_skylake_config { /* Camera */ u8 Cio2Enable; - u8 SaImguEnable; /* eMMC and SD */ u8 ScsEmmcHs400Enabled; |