vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww24 release and adapt soc

The previous Intel CPX-SP FSP release was ww20 release.

The ww22 release fixs issues related to FSP_NV_STORAGE HOB. The end of end
flow of using memory training data to generate FSP_NV_STORAGE HOB and
using memory training data passed from bootloader to skip memory
training, works now. This saves 8 minutes of boot time (with FSP verbose
logging enabled on DeltaLake server).

This release also adds UPD parameters to support IIO bifuration.

The ww24 release has following updates:
a. Removed a number of unnecessary UPD parameters, such as mmiolSize,
mmiolBase, OemHookPostTopologyDiscovery, OemGetResourceMapUpdate.
b. Added UPD parameters to support PCIe ports configuration.
c. Updated IIO_UNIVERSAL_DATA HOB, each stack now has mmio base/limit
fields, in addition to PCIe resource memory base/limit fields.

With ww24 release, the issue with PCIe link training persists. On YV3
config A, the onboard NIC card has x4 connection to port 2D. This
NIC device is not recognized by FSP.

Corresponding soc/intel/xeon_sp/cpx change is made:
* There are changes in PLATFORM_DATA structure, so hob_display.c
is updated.
* There are changes in UPD parameters, so romstage.c is updated.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I70762b377a057d0fca7806f485cce8d479fb5baa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41903
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 8 insertions, 12 deletions

diff --git a/src/soc/intel/xeon_sp/cpx/hob_display.c b/src/soc/intel/xeon_sp/cpx/hob_display.c
index 37c0c7e773..d10a0f6515 100644
--- a/src/soc/intel/xeon_sp/cpx/hob_display.c
+++ b/src/soc/intel/xeon_sp/cpx/hob_display.c
@@ -97,14 +97,14 @@ void soc_display_iio_universal_data_hob(void)
 	printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n");
 	printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase);
 	printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit);
-	printk(BIOS_DEBUG, "\tPlatGlobalMmiolBase: 0x%x\n",
-		hob->PlatformData.PlatGlobalMmiolBase);
-	printk(BIOS_DEBUG, "\tPlatGlobalMmiolLimit: 0x%x\n",
-		hob->PlatformData.PlatGlobalMmiolLimit);
-	printk(BIOS_DEBUG, "\tPlatGlobalMmiohBase: 0x%llx\n",
-		hob->PlatformData.PlatGlobalMmiohBase);
-	printk(BIOS_DEBUG, "\tPlatGlobalMmiohLimit: 0x%llx\n",
-		hob->PlatformData.PlatGlobalMmiohLimit);
+	printk(BIOS_DEBUG, "\tPlatGlobalMmio32Base: 0x%x\n",
+		hob->PlatformData.PlatGlobalMmio32Base);
+	printk(BIOS_DEBUG, "\tPlatGlobalMmio32Limit: 0x%x\n",
+		hob->PlatformData.PlatGlobalMmio32Limit);
+	printk(BIOS_DEBUG, "\tPlatGlobalMmio64Base: 0x%llx\n",
+		hob->PlatformData.PlatGlobalMmio64Base);
+	printk(BIOS_DEBUG, "\tPlatGlobalMmio64Limit: 0x%llx\n",
+		hob->PlatformData.PlatGlobalMmio64Limit);
 	printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize);
 	printk(BIOS_DEBUG, "\tMemIedSize: 0x%x\n", hob->PlatformData.MemIedSize);
 	printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase);
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c
index cbaa006219..4b97ddc96d 100644
--- a/src/soc/intel/xeon_sp/cpx/romstage.c
+++ b/src/soc/intel/xeon_sp/cpx/romstage.c
@@ -33,7 +33,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	/* Bitmask for valid sockets supported by the board */
 	m_cfg->BoardTypeBitmask = 0x11111111;
 
-	m_cfg->mmiolSize = 0x0;
 	m_cfg->mmiohBase = 0x2000;
 
 	/* default: 0x1 (enable), set to 0x2 (auto) */
@@ -65,9 +64,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	/* the wait time in units of 1000us for PBSP to check in */
 	m_cfg->WaitTimeForPSBP = 0x7530;
 
-	m_cfg->OemHookPostTopologyDiscovery = 0xFFF7727B;
-	m_cfg->OemGetResourceMapUpdate = 0xFFF7727C;
-
 	/* Needed to avoid FSP-M reset. The default value of 0x01 is for MinPlatform */
 	m_cfg->PchAdrEn = 0x02;