diff options
| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2021-11-11 18:02:13 +0530 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2021-11-15 10:34:44 +0000 |
| commit | 3b037989537bd45350a41c5ae523f51aa44b492f (patch) | |
| tree | 4c08ccde8b69eabc67665909d9bbdbb4e24c470c /src/soc/intel | |
| parent | f005c34172413e41e85051a945ca6b0aaccc2c46 (diff) | |
soc/intel/alderlake: Disable VT-d for early silicons
VT-d needs to disabled for early silicons as it results in a
CPU hard hang.
BUG=b:197177091
Test=Boot brya to OS with no hang
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index be71a02c0a..121251e7de 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -3,6 +3,7 @@ #include <assert.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/intel/cpu_ids.h> #include <device/device.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> @@ -259,6 +260,14 @@ static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { + const uint32_t cpuid = cpu_get_cpuid(); + + /* Disable VT-d for early silicon steppings as it results in a CPU hard hang */ + if (cpuid == CPUID_ALDERLAKE_A0 || cpuid == CPUID_ALDERLAKE_A1) { + m_cfg->VtdDisable = 1; + return; + } + m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_VTVCO] = VTVC0_BASE_ADDRESS; |