broadwell: Add reporting of broadwell MCH revision

Since the E0 and F0 stepping parts have the same CPUID it is
necessary to use the MCH PCI device revision to determine what
the actual stepping is.

Add this decode table so the early output gives proper identification
of the installed CPU type.

BUG=chrome-os-partner:32359
BRANCH=samus,auron
TEST=build and boot on samus with E0 and F0 parts

Change-Id: Idce1e289cd958c77febc87395f27570247512a87
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a5346141e45b105a35a7641f60b29e02ab2bdfa3
Original-Change-Id: I1bc127badd75ecc34d3d2dbae5d272bd4d9f9082
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223158
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9228
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

2 files changed, 39 insertions, 3 deletions

diff --git a/src/soc/intel/broadwell/broadwell/systemagent.h b/src/soc/intel/broadwell/broadwell/systemagent.h
index c3b5f942e6..61ea56a30a 100644
--- a/src/soc/intel/broadwell/broadwell/systemagent.h
+++ b/src/soc/intel/broadwell/broadwell/systemagent.h
@@ -36,6 +36,11 @@
 #define IGD_BROADWELL_H_GT2	0x1612
 #define IGD_BROADWELL_H_GT3	0x1622
 
+#define MCH_BROADWELL_ID_U_Y	0x1604
+#define MCH_BROADWELL_REV_D0	0x06
+#define MCH_BROADWELL_REV_E0	0x08
+#define MCH_BROADWELL_REV_F0	0x09
+
 /* Device 0:0.0 PCI configuration space */
 
 #define EPBAR		0x40
diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c
index d4355644db..84273e4f3a 100644
--- a/src/soc/intel/broadwell/romstage/report_platform.c
+++ b/src/soc/intel/broadwell/romstage/report_platform.c
@@ -32,7 +32,7 @@
 static struct {
 	u32 cpuid;
 	const char *name;
-} cpu_table [] = {
+} cpu_table[] = {
 	{ CPUID_HASWELL_A0,     "Haswell A0" },
 	{ CPUID_HASWELL_B0,     "Haswell B0" },
 	{ CPUID_HASWELL_C0,     "Haswell C0" },
@@ -45,9 +45,18 @@ static struct {
 };
 
 static struct {
+	u8 revid;
+	const char *name;
+} mch_rev_table[] = {
+	{ MCH_BROADWELL_REV_D0, "Broadwell D0" },
+	{ MCH_BROADWELL_REV_E0, "Broadwell E0" },
+	{ MCH_BROADWELL_REV_F0, "Broadwell F0" },
+};
+
+static struct {
 	u16 lpcid;
 	const char *name;
-} pch_table [] = {
+} pch_table[] = {
 	{ PCH_LPT_LP_SAMPLE,     "LynxPoint LP Sample" },
 	{ PCH_LPT_LP_PREMIUM,    "LynxPoint LP Premium" },
 	{ PCH_LPT_LP_MAINSTREAM, "LynxPoint LP Mainstream" },
@@ -65,7 +74,7 @@ static struct {
 static struct {
 	u16 igdid;
 	const char *name;
-} igd_table [] = {
+} igd_table[] = {
 	{ IGD_HASWELL_ULT_GT1,     "Haswell ULT GT1" },
 	{ IGD_HASWELL_ULT_GT2,     "Haswell ULT GT2" },
 	{ IGD_HASWELL_ULT_GT3,     "Haswell ULT GT3" },
@@ -131,6 +140,27 @@ static void report_cpu_info(void)
 	       "VT %ssupported\n", mode[aes], mode[txt], mode[vt]);
 }
 
+static void report_mch_info(void)
+{
+	int i;
+	u16 mch_device = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID);
+	u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
+	const char *mch_type = "Unknown";
+
+	/* Look for string to match the revision for Broadwell U/Y */
+	if (mch_device == MCH_BROADWELL_ID_U_Y) {
+		for (i = 0; i < ARRAY_SIZE(mch_rev_table); i++) {
+			if (mch_rev_table[i].revid == mch_revision) {
+				mch_type = mch_rev_table[i].name;
+				break;
+			}
+		}
+	}
+
+	printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
+	       mch_device, mch_revision, mch_type);
+}
+
 static void report_pch_info(void)
 {
 	int i;
@@ -166,6 +196,7 @@ static void report_igd_info(void)
 void report_platform_info(void)
 {
 	report_cpu_info();
+	report_mch_info();
 	report_pch_info();
 	report_igd_info();
 }