diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-09-15 12:58:11 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-17 22:22:20 +0000 |
| commit | 0e25580fe1db10cf45f3bb2684e068006a61afe1 (patch) | |
| tree | 437498fbbb3e59addfa117cd1bd2af4c554e450f /src/soc/intel | |
| parent | 1ad9ff815610fd94820a9f1c6d4426ae49ba2846 (diff) | |
soc/intel/{ehl,jsl}: make use of Kconfig options for PRMRR size
Migrate the last two platforms to using Kconfig through
`get_valid_prmrr_size()` instead of hardcoded values in the devicetree.
Change-Id: I93aa177f741ca8b2a2d50fae2515606b96784e83
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/elkhartlake/chip.h | 12 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/romstage/fsp_params.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/chip.h | 12 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/romstage/fsp_params.c | 3 |
4 files changed, 8 insertions, 22 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index b4d5cc045e..b36d67a55f 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -235,17 +235,9 @@ struct soc_intel_elkhartlake_config { /* Enable C6 DRAM */ uint8_t enable_c6dram; - /* - * PRMRR size setting with below options - * Disable: 0x0 - * 32MB: 0x2000000 - * 64MB: 0x4000000 - * 128 MB: 0x8000000 - * 256 MB: 0x10000000 - * 512 MB: 0x20000000 - */ - uint32_t PrmrrSize; + uint8_t PmTimerDisabled; + /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index 449d14ef65..a15b030dd3 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <device/device.h> #include <fsp/util.h> +#include <intelblocks/cpulib.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/romstage.h> @@ -38,7 +39,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, FSP_ARRAY_LOAD(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage); FSP_ARRAY_LOAD(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq); - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->PrmrrSize = get_valid_prmrr_size(); /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 18627f6021..3d680d3b7e 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -151,17 +151,9 @@ struct soc_intel_jasperlake_config { /* Enable C6 DRAM */ uint8_t enable_c6dram; - /* - * PRMRR size setting with below options - * Disable: 0x0 - * 32MB: 0x2000000 - * 64MB: 0x4000000 - * 128 MB: 0x8000000 - * 256 MB: 0x10000000 - * 512 MB: 0x20000000 - */ - uint32_t PrmrrSize; + uint8_t PmTimerDisabled; + /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index 1241b0b72c..fd59e4e89e 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <device/device.h> #include <fsp/util.h> +#include <intelblocks/cpulib.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/romstage.h> @@ -72,7 +73,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, FSP_ARRAY_LOAD(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage); FSP_ARRAY_LOAD(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq); - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->PrmrrSize = get_valid_prmrr_size(); /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; |