diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2015-12-02 11:42:04 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-16 11:59:40 +0100 |
| commit | 086730b0629237c9f171515b82b617ef27f73492 (patch) | |
| tree | 5ae7f3d9d04ffd254c4245ad2376e852c75adab3 /src/soc/intel | |
| parent | 3fc42772bcc97fa6e5ff5235126ff30c359a5b7c (diff) | |
intel/skylake: Add kconfig option to skip Native SD Controller
Skylake Core boot should have configurable option to skip
PCH based SD 3.0 Controller from customer/reference design.
Addition to that no unused or unnecessary should list under
device view.
BUG=chrome-os-partner:48190
BRANCH=None
TEST=Build & boot Kunimitsu and LARs.
Change-Id: Ie17fd6db01e0cabcdf605017509d809b54509a0d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 99ac17b723125822368539d0562aa35119e520fb
Original-Change-Id: I98a48f45ef442246227fd54ea021b53f824954c5
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315420
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12946
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/intel/skylake/acpi/scs.asl | 2 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 76459c9bca..58b828fd17 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -79,6 +79,12 @@ config DCACHE_RAM_SIZE The size of the cache-as-ram region required during bootblock and/or romstage. +config EXCLUDE_NATIVE_SD_INTERFACE + bool + default n + help + If you set this option to n, will not use native SD controller. + config HEAP_SIZE hex default 0x80000 diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index 52eeefe314..56f27a97ea 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -70,6 +70,7 @@ Device (EMMC) } } +#if !IS_ENABLED(CONFIG_EXCLUDE_NATIVE_SD_INTERFACE) Device (SDXC) { Name (_ADR, 0x001E0006) @@ -123,3 +124,4 @@ Device (SDXC) } } } +#endif
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