diff options
| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2023-08-18 14:25:22 -0700 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-10-20 14:32:44 +0000 |
| commit | 052fb7c45136263ed194c24fd4d04488a2608fd3 (patch) | |
| tree | 951b5614c6d21459394a4b6a22d741daa711d6c3 /src/soc/intel | |
| parent | 621ccf8a975de10a641ba36c9f8065b7fb659611 (diff) | |
x86: Add pre-memory stages CBFS cache scratchpad support
Having a CBFS cache scratchpad offers a generic way to decompress CBFS
files through the cbfs_map() function without having to reserve a
per-file specific memory region.
This commit introduces the x86 `PRERAM_CBFS_CACHE_SIZE' Kconfig to set
the pre-memory stages CBFS cache size. A cache size of zero disables
the CBFS cache feature. The default value is 16 KB which seems a
reasonable minimal value enough to satisfy basic needs such as the
decompression of a small configuration file. This setting can be
adjusted depending on the platform needs and capabilities.
We have set this size to zero for all the platforms without enough
space in Cache-As-RAM to accommodate the default size.
TEST=Decompression of vbt.bin in romstage on rex using cbfs_map()
Change-Id: Iee493f9947fddcc57576f04c3d6a2d58c7368e09
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/baytrail/Kconfig | 3 | ||||
| -rw-r--r-- | src/soc/intel/braswell/Kconfig | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 13fd201f9f..dbadbf1105 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -110,6 +110,9 @@ config DCACHE_RAM_SIZE and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2. +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_RAM_MRC_VAR_SIZE hex default 0x8000 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ba6450bec7..5aeb9e56ec 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -97,6 +97,9 @@ config DCACHE_RAM_SIZE and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2. +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n |