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authorLijian Zhao <lijian.zhao@intel.com>2017-07-08 18:16:13 -0700
committerAaron Durbin <adurbin@chromium.org>2017-07-26 21:37:14 +0000
commitc319bab3cd416d85330774f9974b41fcb49075a7 (patch)
tree7533dac79d57499e552393695b5c751a2986eb5c /src/soc/intel
parent735779cc9aa9d6b02fadbdfc0a50fb087cce7731 (diff)
intel/cannonlake_rvp: Split RVP boards and SPD
Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support. Implement SPD entry to FSPM for both platforms, seperated platform specific DQ/DQS/Rcomp input to FSPM as well. Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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