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authorFurquan Shaikh <furquan@google.com>2016-06-01 01:55:43 -0700
committerFurquan Shaikh <furquan@google.com>2016-06-02 17:22:01 +0200
commitb54a2d1d76549fc6dfacb880439d8785a50a589f (patch)
treed8609a33c1631ce70063a2e97dc2b3c021a82af3 /src/soc/intel
parentd5583a5e61c4dbb870ceddc13fbee49b0d46d52f (diff)
intel/apollolake: Add car.c to verstage
Verstage on apollolake requires the functions defined in car.c to perform flush of l1d to l2 on loading romstage into CAR. Change-Id: I6d9a0b9dfb58c2126ad70172846e90663e588857 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15046 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 29636e17b8..9e4e160e35 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -59,6 +59,7 @@ postcar-y += mmap_boot.c
postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
postcar-y += tsc_freq.c
+verstage-y += car.c
verstage-y += memmap.c
verstage-y += mmap_boot.c
verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c