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authorXiang Wang <wxjstz@126.com>2019-06-14 16:45:54 +0800
committerPatrick Rudolph <siro@das-labor.org>2019-06-23 12:14:54 +0000
commitb1e6654d86fff0016651ede345846f4437a2569c (patch)
treeadbddd20616ef26ef52d963fec82bafbebb8015a /src/soc/intel
parent3280aa7df266c964e1b354b18fcd3134f310b776 (diff)
riscv: use mret to invoke M-mode payload and disable interrupts
Fixes a logic error that sets MPIE, but didn't use mret to return to the payload. This left MIE set to an undefined value. Now all modes are handled the same way: - Trap vector base address point to the payload - Disable Interrupt - Return to payload using mret TEST=Run an M-mode payload Change-Id: Iaab595f916949c57104ec00f8b06ea047fe76bba Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33462 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
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