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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-10-22 15:22:46 -0600 |
|---|---|---|
| committer | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-10-25 00:05:23 +0000 |
| commit | 74258d789cf3da7f1885e0fb405eb63205106a9d (patch) | |
| tree | a57eb7f058a216cc5bb85374ae3012e7dd452520 /src/soc/intel | |
| parent | 76118a7d192af29f26fa0dbe85b1cd324cb774d5 (diff) | |
soc/amd/common/pi: Correct top of DRAM reporting by AGESA
Accurately reflect the intention of the syslimit value returned
from AmdInitPost(). Assume FFs for the non-present bits.
BUG=b:118178425
TEST=Boot Grunt and verify reported value = TOM2-1.
Change-Id: Ie8ea4fcbfd52c46ad441890f0decaf0f55816cfd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions