Rename __attribute__((packed)) --> __packed

Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))

Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

44 files changed, 129 insertions, 81 deletions

diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c
index a571a654d6..515d32b99c 100644
--- a/src/soc/intel/apollolake/cse.c
+++ b/src/soc/intel/apollolake/cse.c
@@ -21,6 +21,7 @@
 #include <intelblocks/cse.h>
 #include <soc/pci_devs.h>
 #include <stdint.h>
+#include <compiler.h>
 
 #define PCI_ME_HFSTS1	0x40
 #define PCI_ME_HFSTS2	0x48
@@ -69,7 +70,7 @@ static int read_cse_file(const char *path, void *buff, size_t *size,
 			uint32_t is_response: 1;
 			uint32_t reserved: 8;
 			uint32_t result: 8;
-		} __attribute__ ((packed)) fields;
+		} __packed fields;
 	};
 
 	struct mca_command {
@@ -78,13 +79,13 @@ static int read_cse_file(const char *path, void *buff, size_t *size,
 		uint32_t offset;
 		uint32_t data_size;
 		uint8_t flags;
-	} __attribute__ ((packed)) msg;
+	} __packed msg;
 
 	struct mca_response {
 		union mkhi_header mkhi_hdr;
 		uint32_t data_size;
 		uint8_t buffer[128];
-	} __attribute__ ((packed)) rmsg;
+	} __packed rmsg;
 
 	if (sizeof(rmsg.buffer) < *size) {
 		printk(BIOS_ERR, "internal buffer is too small\n");
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index e0b223fa48..56085b25a6 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -24,6 +24,7 @@
 #ifndef _SOC_APOLLOLAKE_NVS_H_
 #define _SOC_APOLLOLAKE_NVS_H_
 
+#include <compiler.h>
 #include <vendorcode/google/chromeos/gnvs.h>
 
 typedef struct global_nvs_t {
@@ -45,6 +46,6 @@ typedef struct global_nvs_t {
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
 
 #endif	/* _SOC_APOLLOLAKE_NVS_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 6c189198ab..b6b6e7b5e2 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -19,6 +19,7 @@
 #define _SOC_APOLLOLAKE_PM_H_
 
 #include <stdint.h>
+#include <compiler.h>
 #include <arch/acpi.h>
 
 /* ACPI_BASE_ADDRESS */
@@ -201,7 +202,7 @@ struct chipset_power_state {
 	uint32_t gen_pmcon2;
 	uint32_t gen_pmcon3;
 	uint32_t prev_sleep_state;
-} __attribute__((packed));
+} __packed;
 
 int fill_power_state(struct chipset_power_state *ps);
 int chipset_prev_sleep_state(struct chipset_power_state *ps);
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 79b3cfd7f9..24e00df3fd 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -48,6 +48,7 @@
 #include <timestamp.h>
 #include <timer.h>
 #include <delay.h>
+#include <compiler.h>
 #include "chip.h"
 
 static struct chipset_power_state power_state CAR_GLOBAL;
@@ -372,13 +373,13 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	car_set_var(fsp_version, version);
 }
 
-__attribute__ ((weak))
+__attribute__((weak))
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
 
-__attribute__ ((weak))
+__attribute__((weak))
 void mainboard_save_dimm_info(void)
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h
index 5ac95e45b2..b4fe65e7d9 100644
--- a/src/soc/intel/baytrail/include/soc/device_nvs.h
+++ b/src/soc/intel/baytrail/include/soc/device_nvs.h
@@ -17,6 +17,7 @@
 #define _BAYTRAIL_DEVICE_NVS_H_
 
 #include <stdint.h>
+#include <compiler.h>
 
 /* Offset in Global NVS where this structure lives */
 #define DEVICE_NVS_OFFSET	0x1000
@@ -59,6 +60,6 @@ typedef struct {
 	/* Extra */
 	u32	lpe_fw; /* LPE Firmware */
 	u8	rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */
-} __attribute__((packed)) device_nvs_t;
+} __packed device_nvs_t;
 
 #endif
diff --git a/src/soc/intel/baytrail/include/soc/efi_wrapper.h b/src/soc/intel/baytrail/include/soc/efi_wrapper.h
index 3304d03451..3425aae823 100644
--- a/src/soc/intel/baytrail/include/soc/efi_wrapper.h
+++ b/src/soc/intel/baytrail/include/soc/efi_wrapper.h
@@ -29,6 +29,8 @@
 #ifndef __EFI_WRAPPER_H__
 #define __EFI_WRAPPER_H__
 
+#include <compiler.h>
+
 #define EFI_WRAPPER_VER 2
 
 /* Provide generic x86 calling conventions. */
@@ -46,7 +48,7 @@ struct efi_wrapper_params {
 	void ABI_X86 (*console_out)(unsigned char byte);
 
 	unsigned int tsc_ticks_per_microsecond;
-} __attribute__((packed));
+} __packed;
 
 typedef int ABI_X86 (*efi_wrapper_entry_t)(struct efi_wrapper_params *);
 #endif
diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h
index 9c6b7fd025..0e0395a536 100644
--- a/src/soc/intel/baytrail/include/soc/gpio.h
+++ b/src/soc/intel/baytrail/include/soc/gpio.h
@@ -17,6 +17,7 @@
 #define _BAYTRAIL_GPIO_H_
 
 #include <stdint.h>
+#include <compiler.h>
 #include <arch/io.h>
 #include <soc/iomap.h>
 
@@ -352,7 +353,7 @@ struct soc_gpio_map {
 	u32 smi     : 1;
 	u32 is_gpio : 1;
 	u32 sci     : 1;
-} __attribute__ ((packed));
+} __packed;
 
 struct soc_gpio_config {
 	const struct soc_gpio_map *ncore;
diff --git a/src/soc/intel/baytrail/include/soc/mrc_wrapper.h b/src/soc/intel/baytrail/include/soc/mrc_wrapper.h
index 355dce0706..d3547c2fb2 100644
--- a/src/soc/intel/baytrail/include/soc/mrc_wrapper.h
+++ b/src/soc/intel/baytrail/include/soc/mrc_wrapper.h
@@ -28,6 +28,8 @@
 #ifndef _MRC_WRAPPER_H_
 #define _MRC_WRAPPER_H_
 
+#include <compiler.h>
+
 #define MRC_PARAMS_VER  5
 
 #define NUM_CHANNELS 2
@@ -76,7 +78,7 @@ struct mrc_mainboard_params {
 	int dram_odt_value;
 	int spd_addrs[NUM_CHANNELS];
 	void *dram_data[NUM_CHANNELS]; /* SPD or Timing specific data. */
-} __attribute__((packed));
+} __packed;
 
 struct mrc_params {
 	/* Mainboard Inputs */
@@ -99,7 +101,7 @@ struct mrc_params {
 	void *txe_base_address;
 	int data_to_save_size;
 	void *data_to_save;
-} __attribute__((packed));
+} __packed;
 
 /* Call into wrapper. */
 typedef int ABI_X86 (*mrc_wrapper_entry_t)(struct mrc_params *);
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index cb4e9bf18f..8e6819d3b2 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -17,6 +17,7 @@
 #ifndef _BAYTRAIL_NVS_H_
 #define _BAYTRAIL_NVS_H_
 
+#include <compiler.h>
 #include <vendorcode/google/chromeos/gnvs.h>
 #include <soc/device_nvs.h>
 
@@ -64,7 +65,7 @@ typedef struct {
 
 	/* Baytrail LPSS (0x1000) */
 	device_nvs_t dev;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
 
 void acpi_create_gnvs(global_nvs_t *gnvs);
 #ifdef __SMM__
diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h
index c8d6a67a81..1059d3cd6c 100644
--- a/src/soc/intel/baytrail/include/soc/pmc.h
+++ b/src/soc/intel/baytrail/include/soc/pmc.h
@@ -16,6 +16,7 @@
 #ifndef _BAYTRAIL_PMC_H_
 #define _BAYTRAIL_PMC_H_
 
+#include <compiler.h>
 #include <arch/acpi.h>
 
 #define IOCOM1		0x3f8
@@ -262,7 +263,7 @@ struct chipset_power_state {
 	uint32_t prsts;
 	uint32_t gen_pmcon1;
 	uint32_t gen_pmcon2;
-} __attribute__((packed));
+} __packed;
 
 /* Power Management Utility Functions. */
 uint16_t get_pmbase(void);
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index 6061116c52..340c00c27c 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -14,6 +14,7 @@
 
 /* This file is derived from the flashrom project. */
 #include <stdint.h>
+#include <compiler.h>
 #include <stdlib.h>
 #include <string.h>
 #include <bootstate.h>
@@ -93,7 +94,7 @@ typedef struct ich9_spi_regs {
 	uint32_t srdl;
 	uint32_t srdc;
 	uint32_t srd;
-} __attribute__((packed)) ich9_spi_regs;
+} __packed ich9_spi_regs;
 
 typedef struct ich_spi_controller {
 	int locked;
diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h
index 6318918b71..268655e7cb 100644
--- a/src/soc/intel/braswell/include/soc/device_nvs.h
+++ b/src/soc/intel/braswell/include/soc/device_nvs.h
@@ -18,6 +18,7 @@
 #define _SOC_DEVICE_NVS_H_
 
 #include <stdint.h>
+#include <compiler.h>
 
 /* Offset in Global NVS where this structure lives */
 #define DEVICE_NVS_OFFSET	0x1000
@@ -59,6 +60,6 @@ typedef struct {
 
 	/* Extra */
 	u32	lpe_fw; /* LPE Firmware */
-} __attribute__((packed)) device_nvs_t;
+} __packed device_nvs_t;
 
 #endif	/* _SOC_DEVICE_NVS_H_ */
diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h
index 4abc9f47bf..294f176676 100644
--- a/src/soc/intel/braswell/include/soc/gpio.h
+++ b/src/soc/intel/braswell/include/soc/gpio.h
@@ -18,6 +18,7 @@
 #define _SOC_GPIO_H_
 
 #include <stdint.h>
+#include <compiler.h>
 #include <arch/io.h>
 #include <soc/gpio_defs.h>
 #include <soc/iomap.h>
@@ -394,7 +395,7 @@ struct soc_gpio_map {
 	u32 wake_mask:1;
 	u32 is_gpio:1;
 	u32 skip_config:1;
-} __attribute__ ((packed));
+} __packed;
 
 struct soc_gpio_config {
 	const struct soc_gpio_map *north;
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index d3dfd28320..80b0759d76 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -19,6 +19,7 @@
 #define _SOC_NVS_H_
 
 #include <rules.h>
+#include <compiler.h>
 #include <vendorcode/google/chromeos/gnvs.h>
 #include <soc/device_nvs.h>
 
@@ -68,7 +69,7 @@ typedef struct {
 
 	/* LPSS (0x1000) */
 	device_nvs_t dev;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
 
 void acpi_create_gnvs(global_nvs_t *gnvs);
 #if ENV_SMM
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h
index 3d11330efb..5f809edecd 100644
--- a/src/soc/intel/braswell/include/soc/pm.h
+++ b/src/soc/intel/braswell/include/soc/pm.h
@@ -17,6 +17,7 @@
 #ifndef _SOC_PM_H_
 #define _SOC_PM_H_
 
+#include <compiler.h>
 #include <arch/acpi.h>
 
 #define IOCOM1		0x3f8
@@ -221,7 +222,7 @@ struct chipset_power_state {
 	uint32_t gen_pmcon1;
 	uint32_t gen_pmcon2;
 	int prev_sleep_state;
-} __attribute__((packed));
+} __packed;
 
 struct chipset_power_state *fill_power_state(void);
 
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index 4bdcdbff8f..3fc9ba1114 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -26,6 +26,7 @@
 #include <spi_flash.h>
 #include <spi-generic.h>
 #include <stdint.h>
+#include <compiler.h>
 #include <stdlib.h>
 #include <string.h>
 
@@ -80,7 +81,7 @@ typedef struct ich9_spi_regs {
 	uint16_t preop;
 	uint16_t optype;
 	uint8_t opmenu[8];
-} __attribute__((packed)) ich9_spi_regs;
+} __packed ich9_spi_regs;
 
 typedef struct ich_spi_controller {
 	int locked;
diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h
index a436a4c661..15240d13b4 100644
--- a/src/soc/intel/broadwell/include/soc/device_nvs.h
+++ b/src/soc/intel/broadwell/include/soc/device_nvs.h
@@ -17,6 +17,7 @@
 #define _BROADWELL_DEVICE_NVS_H_
 
 #include <stdint.h>
+#include <compiler.h>
 
 /* Offset in Global NVS where this structure lives */
 #define DEVICE_NVS_OFFSET	0x1000
@@ -35,6 +36,6 @@ typedef struct {
 	u8	enable[9];
 	u32	bar0[9];
 	u32	bar1[9];
-} __attribute__((packed)) device_nvs_t;
+} __packed device_nvs_t;
 
 #endif
diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h
index 7aba8dcf60..c8f0300f15 100644
--- a/src/soc/intel/broadwell/include/soc/gpio.h
+++ b/src/soc/intel/broadwell/include/soc/gpio.h
@@ -17,6 +17,7 @@
 #define _BROADWELL_GPIO_H_
 
 #include <stdint.h>
+#include <compiler.h>
 
 #define CROS_GPIO_DEVICE_NAME		"PCH-LP"
 #define CROS_GPIO_ACPI_DEVICE_NAME	"INT3437:00"
@@ -167,7 +168,7 @@ struct gpio_config {
 	u8 reset;
 	u8 blink;
 	u8 pirq;
-} __attribute__ ((packed));
+} __packed;
 
 /* Configure GPIOs with mainboard provided settings */
 void init_one_gpio(int gpio_num, struct gpio_config *config);
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h
index 0d0ad7b3d4..34b44816e8 100644
--- a/src/soc/intel/broadwell/include/soc/me.h
+++ b/src/soc/intel/broadwell/include/soc/me.h
@@ -16,6 +16,7 @@
 #ifndef _BROADWELL_ME_H_
 #define _BROADWELL_ME_H_
 
+#include <compiler.h>
 #include <commonlib/loglevel.h>
 
 #define ME_RETRY		100000	/* 1 second */
@@ -75,7 +76,7 @@ struct me_hfs {
 	u32 boot_options_present: 1;
 	u32 ack_data: 3;
 	u32 bios_msg_ack: 4;
-} __attribute__ ((packed));
+} __packed;
 
 #define PCI_ME_UMA		0x44
 
@@ -85,7 +86,7 @@ struct me_uma {
 	u32 valid: 1;
 	u32 reserved_0: 14;
 	u32 set_to_one: 1;
-} __attribute__ ((packed));
+} __packed;
 
 #define PCI_ME_H_GS		0x4c
 #define  ME_INIT_DONE		1
@@ -104,7 +105,7 @@ struct me_did {
 	u32 rapid_start: 1;
 	u32 status: 4;
 	u32 init_done: 4;
-} __attribute__ ((packed));
+} __packed;
 
 /*
  * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according
@@ -195,7 +196,7 @@ struct me_hfs2 {
 	u32 current_state: 8;
 	u32 current_pmevent: 4;
 	u32 progress_code: 4;
-} __attribute__ ((packed));
+} __packed;
 
 #define PCI_ME_HFS5		0x68
 
@@ -212,7 +213,7 @@ struct me_heres {
 	u32 reserved: 26;
 	u32 extend_feature_present: 1;
 	u32 extend_reg_valid: 1;
-} __attribute__ ((packed));
+} __packed;
 
 /*
  * Management Engine MEI registers
@@ -233,7 +234,7 @@ struct mei_csr {
 	u32 buffer_read_ptr: 8;
 	u32 buffer_write_ptr: 8;
 	u32 buffer_depth: 8;
-} __attribute__ ((packed));
+} __packed;
 
 #define MEI_ADDRESS_CORE	0x01
 #define MEI_ADDRESS_AMT		0x02
@@ -251,7 +252,7 @@ struct mei_header {
 	u32 length: 9;
 	u32 reserved: 6;
 	u32 is_complete: 1;
-} __attribute__ ((packed));
+} __packed;
 
 #define MKHI_GROUP_ID_CBM	0x00
 #define  MKHI_GLOBAL_RESET	0x0b
@@ -274,7 +275,7 @@ struct mkhi_header {
 	u32 is_response: 1;
 	u32 reserved: 8;
 	u32 result: 8;
-} __attribute__ ((packed));
+} __packed;
 
 struct me_fw_version {
 	u16 code_minor;
@@ -285,7 +286,7 @@ struct me_fw_version {
 	u16 recovery_major;
 	u16 recovery_build_number;
 	u16 recovery_hot_fix;
-} __attribute__ ((packed));
+} __packed;
 
 /* ICC Messages */
 #define ICC_SET_CLOCK_ENABLES		0x3
@@ -297,14 +298,14 @@ struct icc_header {
 	u32 icc_status;
 	u32 length;
 	u32 reserved;
-} __attribute__ ((packed));
+} __packed;
 
 struct icc_clock_enables_msg {
 	u32 clock_enables;
 	u32 clock_mask;
 	u32 no_response: 1;
 	u32 reserved: 31;
-} __attribute__ ((packed));
+} __packed;
 
 #define HECI_EOP_STATUS_SUCCESS       0x0
 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
@@ -318,7 +319,7 @@ struct icc_clock_enables_msg {
 struct me_global_reset {
 	u8 request_origin;
 	u8 reset_type;
-} __attribute__ ((packed));
+} __packed;
 
 typedef enum {
 	ME_NORMAL_BIOS_PATH,
@@ -364,21 +365,21 @@ typedef  struct {
 	u32  mbp_size	 : 8;
 	u32  num_entries : 8;
 	u32  rsvd	 : 16;
-} __attribute__ ((packed)) mbp_header;
+} __packed mbp_header;
 
 typedef struct {
 	u32  app_id  : 8;
 	u32  item_id : 8;
 	u32  length  : 8;
 	u32  rsvd    : 8;
-}  __attribute__ ((packed)) mbp_item_header;
+}  __packed mbp_item_header;
 
 typedef struct {
 	u32       major_version  : 16;
 	u32       minor_version  : 16;
 	u32       hotfix_version : 16;
 	u32       build_version  : 16;
-} __attribute__ ((packed)) mbp_fw_version_name;
+} __packed mbp_fw_version_name;
 
 typedef struct {
 	u32  full_net		: 1;
@@ -400,13 +401,13 @@ typedef struct {
 	u32  reserved_4		: 1;
 	u32  wlan		: 1;
 	u32  reserved_5		: 8;
-} __attribute__ ((packed)) mbp_mefwcaps;
+} __packed mbp_mefwcaps;
 
 typedef struct {
 	u16        device_id;
 	u16        fuse_test_flags;
 	u32        umchid[4];
-}  __attribute__ ((packed)) mbp_rom_bist_data;
+}  __packed mbp_rom_bist_data;
 
 typedef struct {
 	u32        key[8];
@@ -424,7 +425,7 @@ typedef struct {
 	u32 image_type:		4;
 	u32 brand:		4;
 	u32 rsvd1:		16;
-}  __attribute__ ((packed)) mbp_me_firmware_type;
+}  __packed mbp_me_firmware_type;
 
 typedef struct {
 	mbp_me_firmware_type rule_data;
@@ -434,7 +435,7 @@ typedef struct {
 typedef struct {
 	u16 icc_start_address;
 	u16 mask;
-} __attribute__ ((packed)) icc_address_mask;
+} __packed icc_address_mask;
 
 typedef struct {
 	u8        num_icc_profiles;
@@ -443,7 +444,7 @@ typedef struct {
 	u8        reserved;
 	u32       icc_reg_bundles;
 	icc_address_mask icc_address_mask[0];
-} __attribute__ ((packed)) mbp_icc_profile;
+} __packed mbp_icc_profile;
 
 typedef struct {
 	u16  lock_state		     : 1;
@@ -452,24 +453,24 @@ typedef struct {
 	u16  flash_wear_out	     : 1;
 	u16  flash_variable_security : 1;
 	u16  reserved		     : 11;
-} __attribute__ ((packed)) tdt_state_flag;
+} __packed tdt_state_flag;
 
 typedef struct {
 	u8           state;
 	u8           last_theft_trigger;
 	tdt_state_flag  flags;
-}  __attribute__ ((packed)) mbp_at_state;
+}  __packed mbp_at_state;
 
 typedef struct {
 	u32 wake_event_mrst_time_ms;
 	u32 mrst_pltrst_time_ms;
 	u32 pltrst_cpurst_time_ms;
-} __attribute__ ((packed)) mbp_plat_time;
+} __packed mbp_plat_time;
 
 typedef struct {
 	u32 device_type : 2;
 	u32 reserved    : 30;
-} __attribute__ ((packed)) mbp_nfc_data;
+} __packed mbp_nfc_data;
 
 typedef struct {
 	mbp_fw_version_name  *fw_version_name;
@@ -489,7 +490,7 @@ struct me_fwcaps {
 	u8 length;
 	mbp_mefwcaps caps_sku;
 	u8 reserved[3];
-} __attribute__ ((packed));
+} __packed;
 
 void intel_me_hsio_version(uint16_t *version, uint16_t *checksum);
 
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 55d6c8b4ea..a7d6d7c9fc 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -17,6 +17,7 @@
 #ifndef _BROADWELL_NVS_H_
 #define _BROADWELL_NVS_H_
 
+#include <compiler.h>
 #include <vendorcode/google/chromeos/gnvs.h>
 #include <soc/device_nvs.h>
 
@@ -56,7 +57,7 @@ typedef struct {
 
 	/* Device specific (0x1000) */
 	device_nvs_t dev;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
 
 void acpi_create_gnvs(global_nvs_t *gnvs);
 #ifdef __SMM__
diff --git a/src/soc/intel/broadwell/include/soc/pei_data.h b/src/soc/intel/broadwell/include/soc/pei_data.h
index 318cb882d8..339dadd4d6 100644
--- a/src/soc/intel/broadwell/include/soc/pei_data.h
+++ b/src/soc/intel/broadwell/include/soc/pei_data.h
@@ -30,6 +30,7 @@
 #define PEI_DATA_H
 
 #include <types.h>
+#include <compiler.h>
 #include <memory_info.h>
 
 #define PEI_VERSION 22
@@ -74,7 +75,7 @@ struct usb2_port_setting {
 	uint8_t enable;
 	uint8_t oc_pin;
 	uint8_t location;
-} __attribute__((packed));
+} __packed;
 
 struct usb3_port_setting {
 	uint8_t enable;
@@ -84,7 +85,7 @@ struct usb3_port_setting {
 	 * Set to 1 if trace length is <= 5 inches
 	 */
 	uint8_t fixed_eq;
-} __attribute__((packed));
+} __packed;
 
 struct pei_data {
 	uint32_t pei_version;
@@ -191,7 +192,7 @@ struct pei_data {
 	void *data_to_save;
 	int data_to_save_size;
 	struct memory_info meminfo;
-} __attribute__((packed));
+} __packed;
 
 typedef struct pei_data PEI_DATA;
 
diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h
index be7e24c087..9a749c9051 100644
--- a/src/soc/intel/broadwell/include/soc/smm.h
+++ b/src/soc/intel/broadwell/include/soc/smm.h
@@ -17,13 +17,14 @@
 #define _BROADWELL_SMM_H_
 
 #include <stdint.h>
+#include <compiler.h>
 #include <cpu/x86/msr.h>
 
 struct ied_header {
 	char signature[10];
 	u32 size;
 	u8 reserved[34];
-} __attribute__ ((packed));
+} __packed;
 
 struct smm_relocation_params {
 	u32 smram_base;
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index a573e32981..eea3ade7f5 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -13,6 +13,7 @@
 
 /* This file is derived from the flashrom project. */
 #include <stdint.h>
+#include <compiler.h>
 #include <stdlib.h>
 #include <string.h>
 #include <bootstate.h>
@@ -92,7 +93,7 @@ typedef struct ich9_spi_regs {
 	uint32_t srdl;
 	uint32_t srdc;
 	uint32_t srd;
-} __attribute__((packed)) ich9_spi_regs;
+} __packed ich9_spi_regs;
 
 typedef struct ich_spi_controller {
 	int locked;
diff --git a/src/soc/intel/common/block/i2c/lpss_i2c.h b/src/soc/intel/common/block/i2c/lpss_i2c.h
index 8a53660fbd..2cb3d5ed52 100644
--- a/src/soc/intel/common/block/i2c/lpss_i2c.h
+++ b/src/soc/intel/common/block/i2c/lpss_i2c.h
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <intelblocks/lpss_i2c.h>
 
 #define LPSS_DEBUG BIOS_NEVER
@@ -65,7 +66,7 @@ struct lpss_i2c_regs {
 	uint32_t comp_param1;
 	uint32_t comp_version;
 	uint32_t comp_type;
-} __attribute__((packed));
+} __packed;
 
 /* Get I2C controller base address */
 uintptr_t lpss_i2c_base_address(unsigned int bus);
diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c
index a58fe221f8..541a7b4d43 100644
--- a/src/soc/intel/common/mma.c
+++ b/src/soc/intel/common/mma.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <bootstate.h>
 #include <cbfs.h>
 #include <cbmem.h>
@@ -31,7 +32,7 @@
 struct mma_data_container {
 	uint32_t mma_signature; /* "MMAD" */
 	uint8_t mma_data[0]; /* Variable size, platform/run time dependent. */
-} __attribute__ ((packed));
+} __packed;
 
 /*
  * Format of the MMA test metadata file, stored under CBFS
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c
index e0d4b7de01..3ad4cb0d6e 100644
--- a/src/soc/intel/common/mrc_cache.c
+++ b/src/soc/intel/common/mrc_cache.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <compiler.h>
 #include <string.h>
 #include <boot_device.h>
 #include <bootstate.h>
@@ -40,7 +41,7 @@ struct mrc_metadata {
 	uint16_t data_checksum;
 	uint16_t header_checksum;
 	uint32_t version;
-} __attribute__((packed));
+} __packed;
 
 enum result {
 	UPDATE_FAILURE		= -1,
diff --git a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
index 5c4e49bb80..5bafea6fd0 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
@@ -17,6 +17,7 @@
 #define _BAYTRAIL_DEVICE_NVS_H_
 
 #include <stdint.h>
+#include <compiler.h>
 
 /* Offset in Global NVS where this structure lives */
 #define DEVICE_NVS_OFFSET	0x1000
@@ -59,6 +60,6 @@ typedef struct {
 	/* Extra */
 	u32	lpe_fw; /* LPE Firmware */
 	u8	rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */
-} __attribute__((packed)) device_nvs_t;
+} __packed device_nvs_t;
 
 #endif
diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h
index 165443e08a..02c226b1d7 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h
@@ -17,6 +17,7 @@
 #define _BAYTRAIL_GPIO_H_
 
 #include <stdint.h>
+#include <compiler.h>
 #include <arch/io.h>
 #include <soc/iomap.h>
 
@@ -328,7 +329,7 @@ struct soc_gpio_map {
 	u32 smi     : 1;
 	u32 is_gpio : 1;
 	u32 sci     : 1;
-} __attribute__ ((packed));
+} __packed;
 
 struct soc_gpio_config {
 	const struct soc_gpio_map *ncore;
diff --git a/src/soc/intel/fsp_baytrail/include/soc/nvs.h b/src/soc/intel/fsp_baytrail/include/soc/nvs.h
index 17c60ddcf7..f0bf888add 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/nvs.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/nvs.h
@@ -17,6 +17,7 @@
 #ifndef _BAYTRAIL_NVS_H_
 #define _BAYTRAIL_NVS_H_
 
+#include <compiler.h>
 #include <soc/device_nvs.h>
 
 typedef struct {
@@ -62,7 +63,7 @@ typedef struct {
 
 	/* Baytrail LPSS (0x1000) */
 	device_nvs_t dev;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
 
 void acpi_create_gnvs(global_nvs_t *gnvs);
 #ifdef __SMM__
diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h
index d5b1c44cc5..9bafdc2fcf 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h
@@ -17,6 +17,7 @@
 #ifndef _BAYTRAIL_PMC_H_
 #define _BAYTRAIL_PMC_H_
 
+#include <compiler.h>
 #include <arch/acpi.h>
 
 #define IOCOM1		0x3f8
@@ -264,7 +265,7 @@ struct chipset_power_state {
 	uint32_t prsts;
 	uint32_t gen_pmcon1;
 	uint32_t gen_pmcon2;
-} __attribute__((packed));
+} __packed;
 
 /* Power Management Utility Functions. */
 uint16_t get_pmbase(void);
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index 0a04b9ba5f..96e0671c4a 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -16,6 +16,7 @@
 
 /* This file is derived from the flashrom project. */
 #include <stdint.h>
+#include <compiler.h>
 #include <stdlib.h>
 #include <string.h>
 #include <commonlib/helpers.h>
@@ -93,7 +94,7 @@ typedef struct ich9_spi_regs {
 	uint32_t srdl;
 	uint32_t srdc;
 	uint32_t srd;
-} __attribute__((packed)) ich9_spi_regs;
+} __packed ich9_spi_regs;
 
 typedef struct ich_spi_controller {
 	int locked;
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
index ab8ca8eb71..2a737aca18 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/smm.h
@@ -18,13 +18,14 @@
 #define _BROADWELL_SMM_H_
 
 #include <stdint.h>
+#include <compiler.h>
 #include <cpu/x86/msr.h>
 
 struct ied_header {
 	char signature[10];
 	u32 size;
 	u8 reserved[34];
-} __attribute__ ((packed));
+} __packed;
 
 struct smm_relocation_params {
 	u32 smram_base;
diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c
index b917142722..b87ae90bc5 100644
--- a/src/soc/intel/fsp_broadwell_de/spi.c
+++ b/src/soc/intel/fsp_broadwell_de/spi.c
@@ -16,6 +16,7 @@
 
 /* This file is derived from the flashrom project. */
 #include <stdint.h>
+#include <compiler.h>
 #include <stdlib.h>
 #include <string.h>
 #include <delay.h>
@@ -91,7 +92,7 @@ typedef struct ich9_spi_regs {
 	uint32_t srdl;
 	uint32_t srdc;
 	uint32_t srd;
-} __attribute__((packed)) ich9_spi_regs;
+} __packed ich9_spi_regs;
 
 typedef struct ich_spi_controller {
 	int locked;
diff --git a/src/soc/intel/quark/include/soc/pei_wrapper.h b/src/soc/intel/quark/include/soc/pei_wrapper.h
index 5328e76e06..9e63a72ead 100644
--- a/src/soc/intel/quark/include/soc/pei_wrapper.h
+++ b/src/soc/intel/quark/include/soc/pei_wrapper.h
@@ -31,6 +31,7 @@
 #define _PEI_WRAPPER_H_
 
 #include <types.h>
+#include <compiler.h>
 
 #define PEI_VERSION 22
 
@@ -53,7 +54,7 @@ struct pei_data {
 	/* Data from MRC that should be saved to flash */
 	void *data_to_save;
 	int data_to_save_size;
-} __attribute__((packed));
+} __packed;
 
 typedef struct pei_data PEI_DATA;
 
diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h
index 55e5e956aa..ae19cc6c9d 100644
--- a/src/soc/intel/quark/include/soc/pm.h
+++ b/src/soc/intel/quark/include/soc/pm.h
@@ -18,11 +18,12 @@
 #define _SOC_PM_H_
 
 #include <stdint.h>
+#include <compiler.h>
 #include <arch/acpi.h>
 
 struct chipset_power_state {
 	uint32_t prev_sleep_state;
-} __attribute__ ((packed));
+} __packed;
 
 struct chipset_power_state *get_power_state(void);
 #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
diff --git a/src/soc/intel/sch/nvs.h b/src/soc/intel/sch/nvs.h
index 88c4998094..f62715ef92 100644
--- a/src/soc/intel/sch/nvs.h
+++ b/src/soc/intel/sch/nvs.h
@@ -16,6 +16,7 @@
 #ifndef SOC_INTEL_SCH_NVS_H
 #define SOC_INTEL_SCH_NVS_H
 
+#include <compiler.h>
 typedef struct {
 	/* Miscellaneous */
 	u16	osys; /* 0x00 - Operating System */
@@ -133,7 +134,7 @@ typedef struct {
 	u8	dock; /* 0xf0 - Docking Status */
 	u8	bten;
 	u8	rsvd13[14];
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
 
 void acpi_create_gnvs(global_nvs_t * gnvs);
 
diff --git a/src/soc/intel/sch/raminit.h b/src/soc/intel/sch/raminit.h
index 4a81ec1580..0d4f436726 100644
--- a/src/soc/intel/sch/raminit.h
+++ b/src/soc/intel/sch/raminit.h
@@ -16,6 +16,8 @@
 #ifndef RAMINIT_H
 #define RAMINIT_H
 
+#include <compiler.h>
+
 /**
  * Bit Equates
  **/
@@ -171,7 +173,7 @@ struct sys_info {
 	u8 ram_param_source;    /*DRAM Parameter Source SPD/SoftStraps(R) Block (down memory) */
 	u8 boot_path;
 
-} __attribute__ ((packed));
+} __packed;
 
 void sdram_initialize(int boot_mode);
 
diff --git a/src/soc/intel/skylake/include/soc/device_nvs.h b/src/soc/intel/skylake/include/soc/device_nvs.h
index 79b516d9b5..02c9e65809 100644
--- a/src/soc/intel/skylake/include/soc/device_nvs.h
+++ b/src/soc/intel/skylake/include/soc/device_nvs.h
@@ -18,6 +18,7 @@
 #define _SOC_DEVICE_NVS_H_
 
 #include <stdint.h>
+#include <compiler.h>
 
 /* Offset in Global NVS where this structure lives */
 #define DEVICE_NVS_OFFSET	0x1000
@@ -38,6 +39,6 @@ typedef struct {
 	u8	enable[11];
 	u32	bar0[11];
 	u32	bar1[11];
-} __attribute__((packed)) device_nvs_t;
+} __packed device_nvs_t;
 
 #endif
diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h
index 2736d1a04f..e88711ddf3 100644
--- a/src/soc/intel/skylake/include/soc/me.h
+++ b/src/soc/intel/skylake/include/soc/me.h
@@ -18,6 +18,8 @@
 #ifndef _SKYLAKE_ME_H_
 #define _SKYLAKE_ME_H_
 
+#include <compiler.h>
+
 /*
  * Management Engine PCI registers
  */
@@ -68,7 +70,7 @@ union me_hfs {
 	u32 current_power_source: 2;
 	u32 d3_support_valid: 1;
 	u32 d0i3_support_valid: 1;
-	} __attribute__ ((packed)) fields;
+	} __packed fields;
 };
 
 #define PCI_ME_HFSTS2		0x48
@@ -166,7 +168,7 @@ union me_hfs2 {
 	u32 current_state: 8;
 	u32 current_pmevent: 4;
 	u32 progress_code: 4;
-	} __attribute__ ((packed)) fields;
+	} __packed fields;
 };
 
 #define PCI_ME_HFSTS3			0x60
@@ -183,7 +185,7 @@ union me_hfs3 {
 	u32 reserved2: 21;
 	u32 encrypt_key_override: 1;
 	u32 power_down_mitigation: 1;
-	} __attribute__ ((packed)) fields;
+	} __packed fields;
 };
 
 #define PCI_ME_HFSTS6			0x6c
@@ -195,7 +197,7 @@ union me_hfs6 {
 	struct {
 		u32 reserved1: 30;
 		u32 fpf_nvars: 2;
-	} __attribute__ ((packed)) fields;
+	} __packed fields;
 };
 
 /*
@@ -216,7 +218,7 @@ union host_csr {
 	u32 host_read_offset: 8;
 	u32 host_write_offset: 8;
 	u32 me_cir_depth: 8;
-	} __attribute__ ((packed)) fields;
+	} __packed fields;
 };
 
 #define MMIO_ME_CB_RW	0x08
@@ -234,7 +236,7 @@ union me_csr {
 	u32 me_read_offset: 8;
 	u32 me_write_offset: 8;
 	u32 me_cir_buff: 8;
-	} __attribute__ ((packed)) fields;
+	} __packed fields;
 };
 
 #define MMIO_ME_D0I3	0x800
@@ -265,7 +267,7 @@ union mei_header {
 	u32 length: 9;
 	u32 reserved: 6;
 	u32 is_complete: 1;
-	} __attribute__ ((packed)) fields;
+	} __packed fields;
 };
 
 void intel_me_status(void);
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index f72616f05e..4ca3d227b0 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -19,6 +19,7 @@
 #define _SOC_NVS_H_
 
 #include <rules.h>
+#include <compiler.h>
 #include <vendorcode/google/chromeos/gnvs.h>
 
 typedef struct {
@@ -60,7 +61,7 @@ typedef struct {
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;
-} __attribute__((packed)) global_nvs_t;
+} __packed global_nvs_t;
 
 #if ENV_SMM
 /* Used in SMM to find the ACPI GNVS address */
diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h
index be8ba79b92..58485837c6 100644
--- a/src/soc/intel/skylake/include/soc/pei_data.h
+++ b/src/soc/intel/skylake/include/soc/pei_data.h
@@ -31,6 +31,7 @@
 #define _PEI_DATA_H_
 
 #include <types.h>
+#include <compiler.h>
 
 #define PEI_VERSION 22
 
@@ -92,7 +93,7 @@ struct pei_data {
 	void *data_to_save;
 	int data_to_save_size;
 	int mem_cfg_id;
-} __attribute__((packed));
+} __packed;
 
 typedef struct pei_data PEI_DATA;
 
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 15c291cc96..67b1f438b6 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -17,6 +17,7 @@
 #ifndef _SOC_PM_H_
 #define _SOC_PM_H_
 
+#include <compiler.h>
 #include <arch/acpi.h>
 #include <arch/io.h>
 #include <soc/pmc.h>
@@ -147,7 +148,7 @@ struct chipset_power_state {
 	uint32_t gen_pmcon_b;
 	uint32_t gblrst_cause[2];
 	uint32_t prev_sleep_state;
-} __attribute__ ((packed));
+} __packed;
 
 struct chipset_power_state *fill_power_state(void);
 
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index 6ba6fdb72c..06c4aacd3d 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -18,6 +18,7 @@
 #define _SOC_SMM_H_
 
 #include <stdint.h>
+#include <compiler.h>
 #include <cpu/x86/msr.h>
 #include <fsp/memmap.h>
 #include <soc/gpio.h>
@@ -26,7 +27,7 @@ struct ied_header {
 	char signature[10];
 	u32 size;
 	u8 reserved[34];
-} __attribute__ ((packed));
+} __packed;
 
 struct smm_relocation_params {
 	u32 smram_base;
diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c
index 1865c00f7e..bf826ede77 100644
--- a/src/soc/intel/skylake/me.c
+++ b/src/soc/intel/skylake/me.c
@@ -20,6 +20,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <stdint.h>
+#include <compiler.h>
 #include <stdlib.h>
 #include <string.h>
 #include <soc/iomap.h>
@@ -650,7 +651,7 @@ static int send_heci_reset_message(void)
 		u8 command;
 		u8 reserved;
 		u8 result;
-	} __attribute__ ((packed)) reply;
+	} __packed reply;
 	struct reset_message {
 		u8 group_id;
 		u8 cmd;
@@ -658,7 +659,7 @@ static int send_heci_reset_message(void)
 		u8 result;
 		u8 req_origin;
 		u8 reset_type;
-	} __attribute__ ((packed));
+	} __packed;
 	struct reset_message msg = {
 		.cmd = MKHI_GLOBAL_RESET,
 		.req_origin = GR_ORIGIN_BIOS_POST,