diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-07-15 13:31:09 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-19 20:20:13 +0200 |
| commit | 64011880240cea5a3f8b1177853c7992a2d99ea8 (patch) | |
| tree | 6f06cd735d182511d022d551d4a31d78185930a0 /src/soc/intel | |
| parent | fcd51ffae86752f2794e1e5998b84f7119b7f091 (diff) | |
soc/intel/common: Add reset_prepare() for common reset
Some Intel SoC may need preparation before reset can be properly
handled. Add callback that chip/soc code can implement.
BUG=chrome-os-partner:55055
Change-Id: I45857838e1a306dbcb9ed262b55e7db88a8944e5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15720
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/reset.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c index 79547c6edb..08f36b6560 100644 --- a/src/soc/intel/common/reset.c +++ b/src/soc/intel/common/reset.c @@ -25,8 +25,17 @@ #define RST_CPU (1 << 2) #define SYS_RST (1 << 1) +#ifdef __ROMCC__ +#define WEAK +#else +#define WEAK __attribute__((weak)) +#endif + +void WEAK reset_prepare(void) { /* do nothing */ } + void hard_reset(void) { + reset_prepare(); /* S0->S5->S0 trip. */ outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT); while (1) @@ -35,6 +44,7 @@ void hard_reset(void) void soft_reset(void) { + reset_prepare(); /* PMC_PLTRST# asserted. */ outb(RST_CPU | SYS_RST, RST_CNT); while (1) @@ -43,6 +53,7 @@ void soft_reset(void) void cpu_reset(void) { + reset_prepare(); /* Sends INIT# to CPU */ outb(RST_CPU, RST_CNT); while (1) |