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authorFelix Singer <felix.singer@9elements.com>2019-03-13 05:06:06 +0100
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2019-03-25 17:28:17 +0000
commit4e11bff0cfee7e7bd3367099b6daf61f6179043d (patch)
tree8ce8718ebca4f06873d4ee036ca58fd33c554e34 /src/soc/intel
parent5d1f9a009647c741e8587015b14f1e852e1c489e (diff)
soc/apollolake: Add UART0
In my case, on UPsquared board with Celeron N3350 CPU, I don't have UART2 but UART0. Change-Id: Id9a742144eba0f1d1544aafecf44d4730d055b4a Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/uart.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c
index a85ad1f6b9..e8e2661243 100644
--- a/src/soc/intel/apollolake/uart.c
+++ b/src/soc/intel/apollolake/uart.c
@@ -49,6 +49,13 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
#else
{
+ .console_index = 0,
+ .gpios = {
+ PAD_CFG_NF(GPIO_38, NATIVE, DEEP, NF1), /* UART0 RX */
+ PAD_CFG_NF(GPIO_39, NATIVE, DEEP, NF1), /* UART0 TX */
+ },
+ },
+ {
.console_index = 1,
.gpios = {
PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */