diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-25 15:11:15 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-28 08:52:42 +0000 |
| commit | 4a6c0a368e96e393ef48606d6be30bbd9aee2d36 (patch) | |
| tree | 78a5de1d840a6332cdce71ef2d4e1e6b99b40564 /src/soc/intel | |
| parent | 9f78127b61632cbb138bdbfa650c2e9965440d3b (diff) | |
broadwell: Factor out PIRQ routing from devicetree
All boards disable PIRQs, except purism/librem_bdw. Since IRQ0 is
invalid and modern OSes don't use PIRQ routing, disable the PIRQs.
Change-Id: I93b074474c3c6d4329903cab928dc41e1d3a3fb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/broadwell/chip.h | 13 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/lpc.c | 27 |
2 files changed, 11 insertions, 29 deletions
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 45f91d8aef..554399823a 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -8,19 +8,6 @@ #include <stdint.h> struct soc_intel_broadwell_config { - /* - * Interrupt Routing configuration - * If bit7 is 1, the interrupt is disabled. - */ - uint8_t pirqa_routing; - uint8_t pirqb_routing; - uint8_t pirqc_routing; - uint8_t pirqd_routing; - uint8_t pirqe_routing; - uint8_t pirqf_routing; - uint8_t pirqg_routing; - uint8_t pirqh_routing; - /* GPE configuration */ uint32_t gpe0_en_1; uint32_t gpe0_en_2; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 58cd35d1f6..b3f4fe5b2a 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -90,17 +90,18 @@ static void enable_hpet(struct device *dev) static void pch_pirq_init(struct device *dev) { struct device *irq_dev; - config_t *config = config_of(dev); - pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); - pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); - pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); - pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + const uint8_t pirq = 0x80; + + pci_write_config8(dev, PIRQA_ROUT, pirq); + pci_write_config8(dev, PIRQB_ROUT, pirq); + pci_write_config8(dev, PIRQC_ROUT, pirq); + pci_write_config8(dev, PIRQD_ROUT, pirq); - pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); - pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); - pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); - pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + pci_write_config8(dev, PIRQE_ROUT, pirq); + pci_write_config8(dev, PIRQF_ROUT, pirq); + pci_write_config8(dev, PIRQG_ROUT, pirq); + pci_write_config8(dev, PIRQH_ROUT, pirq); for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin = 0, int_line = 0; @@ -112,16 +113,10 @@ static void pch_pirq_init(struct device *dev) switch (int_pin) { case 1: /* INTA# */ - int_line = config->pirqa_routing; - break; case 2: /* INTB# */ - int_line = config->pirqb_routing; - break; case 3: /* INTC# */ - int_line = config->pirqc_routing; - break; case 4: /* INTD# */ - int_line = config->pirqd_routing; + int_line = pirq; break; } |