summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorrobbie zhang <robbie.zhang@intel.com>2015-10-01 16:37:58 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-10-27 15:15:15 +0100
commit32074149f702d988e07753b5ff5633dbd0e3409c (patch)
treee95e5dba17e4e54342ea3d1f93836b9262b3b09a /src/soc/intel
parent246115eb01fff9f97d7932b7349be92ca86b4feb (diff)
fsp/intel common: Add support for Gfx PEIM (AKA GOP)
This patch provides the lb_framebuffer() for coreboot table with fsp gop usage, add Igd Opregion register defines, and update the UPD naming following fsp. BRANCH=none BUG=chrome-os-partner:44559 TEST=Built and boot on kunimitsu/glados. Change-Id: I9cf9d991eb09d698e7a78323cd855c4c99b55eca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd6834057cca60716bc0e24cfc2cd60fed02be7a Original-Change-Id: I64987e393c39a7cc1084edf59e7ca51b8c5ea743 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303539 Original-Commit-Ready: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12141 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/gma.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h
index 03ecedb5da..64b2a2811e 100644
--- a/src/soc/intel/common/gma.h
+++ b/src/soc/intel/common/gma.h
@@ -23,6 +23,12 @@
#include <types.h>
+/* IGD PCI Configuration register */
+#define ASLS 0xfc /* OpRegion Base */
+#define SWSCI 0xe8 /* SWSCI Register */
+#define GSSCIE (1 << 0) /* SCI Event trigger */
+#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */
+
/* mailbox 0: header */
typedef struct {
u8 signature[16];