diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-07-29 14:21:55 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-08-02 04:34:55 +0000 |
| commit | 06cc764483d1220aeed28ff1097e6d517f51b0dd (patch) | |
| tree | f463951b0ab2e6aa2a3ecca209d7a1a597a322f2 /src/soc/intel | |
| parent | ed9ea86ba34252bcd1cd7b6f027d2ff9fe3b6d6b (diff) | |
soc/intel/cannonlake: Disable ACPI PM timer to reduce S0ix power usage
This patch overrides EnableTcoTimer FSP UPD default value based on
PmTimerDisabled coreboot devcietree config.
BRANCH=none
BUG=b:138152075
Change-Id: I347c15c7b65fb4c19b9680f127980d4ddab8df51
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index f696f79d04..3cc426a942 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -367,6 +367,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPwrOptEnable = config->dmipwroptimize; params->SataPwrOptEnable = config->satapwroptimize; + /* Disable PCH ACPI timer */ + params->EnableTcoTimer = !config->PmTimerDisabled; + /* Apply minimum assertion width settings if non-zero */ if (config->PchPmSlpS3MinAssert) params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert; |