diff options
| author | Raul Rangel <rrangel@chromium.org> | 2019-01-17 21:39:19 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-21 13:27:47 +0000 |
| commit | 034e5e6fa5499e52c51097047a8896da734e08ea (patch) | |
| tree | 79810423d764fe32a4665f176de2ff3c7f287ccf /src/soc/intel | |
| parent | da02719462bc1b89405d7aeb799d5d6487aca71a (diff) | |
Revert "soc/amd/stoneyridge/gpio: Configure debounce for irq gpios"
This reverts commit b82afce18aff24b6e5e3b73a67a6533cc4865a26.
Reason for revert: This causes depthcharge to not boot due to TPM timeout errors. Because there is no wait after setting the debounce register, we lose data because the read-modify-write loses the interrupt status bit.
e.g., GPIO 5 sets debounce, without a wait. Then GPIO 9 has it's debounce set. Because the interrupt controller is masking the interrupt enable status bit, the read-modify-write for GPIO9 loses the interrupt enable status bit and it never gets set again. This causes the interrupt to never latch.
We should possibly make depthcharge set the interrupt enable status bit for latched GPIOs.
Change-Id: Idd7259b14b24c441529d64e173be9faec03f4fc8
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/30981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions