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authorXiang Wang <wxjstz@126.com>2019-02-19 15:59:48 +0800
committerPatrick Rudolph <siro@das-labor.org>2019-06-23 12:15:23 +0000
commite56fb89e7c04655ec0fed36484d9e509e08f662f (patch)
tree1ad9999b43303cd5ed06b8efe65aa58597fe18db /src/soc/intel
parentb1e6654d86fff0016651ede345846f4437a2569c (diff)
riscv: workaround selfboot putting the coreboot table into prog_entry_arg
On RISC-V the argument to a payload is always the hartid and a pointer to a FDT. selfboot sets the coreboot tables as an argument, work around this here. Change-Id: If6929897c7f12d8acb079eeebaef512ae506ca8b Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31477 Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
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