diff options
| author | John Zhao <john.zhao@intel.com> | 2020-03-12 15:49:12 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-16 14:46:08 +0000 |
| commit | b159d443dd6e2bd977d30b3cb5db86b38430c1ea (patch) | |
| tree | 70031148f993a0f614529d0bec4d4108121c7d24 /src/soc/intel | |
| parent | b4d9f229d4485c8cd42e7f1e07e2c592729e18b6 (diff) | |
src/soc/tigerlake_dev: Update PMC IPC Hardware ID
Change PMC IPC HID from INT34D2 to INTC1026 along with
new kernel pmc ipc driver.
BUG=b:148949891
BRANCH=none
TEST=Boot on Volteer and validate DP tunneling.
Change-Id: I987e7bf76ad1f8ff534101c80661f7c027a60b51
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/pmc.asl | 32 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/southbridge.asl | 5 |
2 files changed, 36 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/acpi/pmc.asl b/src/soc/intel/tigerlake/acpi/pmc.asl new file mode 100644 index 0000000000..0d62edd926 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/pmc.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/iomap.h> + +Scope (\_SB.PCI0) { + + Device (PMC) + { + Name (_HID, "INTC1026") + Name (_DDN, "Intel(R) Tiger Lake IPC Controller") + /* + * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF. + * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR. + */ + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x00010000) + }) + } +} diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 8593d07326..9d25a735f5 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -40,6 +40,9 @@ /* PCIE Ports */ #include "pcie.asl" +/* pmc 0:1f.2 */ +#include "pmc.asl" + /* Serial IO */ #include "serialio.asl" |