diff options
| author | Furquan Shaikh <furquan@google.com> | 2018-06-28 22:16:12 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-07-25 18:52:47 +0000 |
| commit | 9c462c617ea71f3e007057f09a88152e25c665e0 (patch) | |
| tree | 2fee02d18065fde016566bd0651266c46ceec100 /src/soc/intel | |
| parent | d7b88dcbcd1a8c58cb7a4c806df7bb8eb23899ae (diff) | |
soc/intel/apollolake: Get rid of power button device in coreboot
As per the ACPI specification, there are two types of power button
devices:
1. Fixed hardware power button
2. Generic hardware power button
Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
is not set in FADT by the BIOS. This device has its programming model
in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
power button device by default if the power button FADT flag is not
set.
On the other hand, generic hardware power button can be used by
platforms if fixed register space cannot be used for the power button
device. In order to support this, power button device object with HID
PNP0C0C is expected to be added to ACPI tables. Additionally,
POWER_BUTTON flag should be set to indicate the presence of control
method for power button.
Chrome EC mainboards implemented the generic hardware power button in
a broken manner i.e. power button object with HID PNP0C0C is added to
ACPI however none of the boards set POWER_BUTTON flag in FADT. This
results in Linux kernel adding both fixed hardware power button as
well as generic hardware power button to the list of devices present
on the system. Though this is mostly harmless, it is logically
incorrect and can confuse any userspace utilities scanning the ACPI
devices.
This change gets rid of the generic hardware power button from APL
and relies completely on the fixed hardware power button.
BUG=b:110913245
TEST=Verified that fixed hardware power button still works as expected
on octopus.
Change-Id: I86259465c6cfaf579dd7dc3560b4c9e676b80b55
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27273
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/southbridge.asl | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 5b8f9b7aa6..9f14db48b4 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -18,15 +18,6 @@ #include <intelblocks/pcr.h> #include <soc/gpe.h> -/* Power button. */ -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } -} - /* PCIE device */ #include "pcie.asl" |