diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-12 17:46:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-27 10:25:03 +0000 |
| commit | 4abc73183134def757c553aa4eb195fffa824100 (patch) | |
| tree | e6fa253f8e7dc46e80a0a33ea903b4fe0be83419 /src/soc/intel | |
| parent | aeffa86cc551110b62074fa6302f4960d87a9a8c (diff) | |
ACPI: Separate device_nvs_t
Remove typedef device_nvs_t and move struct device_nvs
outside of global_nvs. Also remove padding and the reserve
for chromeos_acpi_t.
Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel')
27 files changed, 245 insertions, 284 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index bd9f78e3ba..33923d0dc0 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -8,6 +8,7 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_HAS_DEVICE_NVS select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES diff --git a/src/soc/intel/baytrail/acpi/device_nvs.asl b/src/soc/intel/baytrail/acpi/device_nvs.asl index 3722856331..aa0e9533f8 100644 --- a/src/soc/intel/baytrail/acpi/device_nvs.asl +++ b/src/soc/intel/baytrail/acpi/device_nvs.asl @@ -1,68 +1,74 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Device Enabled in ACPI Mode */ +External (NVSD) -S0EN, 8, /* SDMA Enable */ -S1EN, 8, /* I2C1 Enable */ -S2EN, 8, /* I2C2 Enable */ -S3EN, 8, /* I2C3 Enable */ -S4EN, 8, /* I2C4 Enable */ -S5EN, 8, /* I2C5 Enable */ -S6EN, 8, /* I2C6 Enable */ -S7EN, 8, /* I2C7 Enable */ -S8EN, 8, /* SDMA2 Enable */ -S9EN, 8, /* SPI Enable */ -SAEN, 8, /* PWM1 Enable */ -SBEN, 8, /* PWM2 Enable */ -SCEN, 8, /* UART2 Enable */ -SDEN, 8, /* UART2 Enable */ -C0EN, 8, /* MMC Enable */ -C1EN, 8, /* SDIO Enable */ -C2EN, 8, /* SD Card Enable */ -LPEN, 8, /* LPE Enable */ +OperationRegion (DNVS, SystemMemory, NVSD, 0x1000) +Field (DNVS, ByteAcc, NoLock, Preserve) +{ + /* Device Enabled in ACPI Mode */ -/* BAR 0 */ + S0EN, 8, /* SDMA Enable */ + S1EN, 8, /* I2C1 Enable */ + S2EN, 8, /* I2C2 Enable */ + S3EN, 8, /* I2C3 Enable */ + S4EN, 8, /* I2C4 Enable */ + S5EN, 8, /* I2C5 Enable */ + S6EN, 8, /* I2C6 Enable */ + S7EN, 8, /* I2C7 Enable */ + S8EN, 8, /* SDMA2 Enable */ + S9EN, 8, /* SPI Enable */ + SAEN, 8, /* PWM1 Enable */ + SBEN, 8, /* PWM2 Enable */ + SCEN, 8, /* UART2 Enable */ + SDEN, 8, /* UART2 Enable */ + C0EN, 8, /* MMC Enable */ + C1EN, 8, /* SDIO Enable */ + C2EN, 8, /* SD Card Enable */ + LPEN, 8, /* LPE Enable */ -S0B0, 32, /* SDMA BAR0 */ -S1B0, 32, /* I2C1 BAR0 */ -S2B0, 32, /* I2C2 BAR0 */ -S3B0, 32, /* I2C3 BAR0 */ -S4B0, 32, /* I2C4 BAR0 */ -S5B0, 32, /* I2C5 BAR0 */ -S6B0, 32, /* I2C6 BAR0 */ -S7B0, 32, /* I2C7 BAR0 */ -S8B0, 32, /* SDMA2 BAR0 */ -S9B0, 32, /* SPI BAR0 */ -SAB0, 32, /* PWM1 BAR0 */ -SBB0, 32, /* PWM2 BAR0 */ -SCB0, 32, /* UART1 BAR0 */ -SDB0, 32, /* UART2 BAR0 */ -C0B0, 32, /* MMC BAR0 */ -C1B0, 32, /* SDIO BAR0 */ -C2B0, 32, /* SD Card BAR0 */ -LPB0, 32, /* LPE BAR0 */ + /* BAR 0 */ -/* BAR 1 */ + S0B0, 32, /* SDMA BAR0 */ + S1B0, 32, /* I2C1 BAR0 */ + S2B0, 32, /* I2C2 BAR0 */ + S3B0, 32, /* I2C3 BAR0 */ + S4B0, 32, /* I2C4 BAR0 */ + S5B0, 32, /* I2C5 BAR0 */ + S6B0, 32, /* I2C6 BAR0 */ + S7B0, 32, /* I2C7 BAR0 */ + S8B0, 32, /* SDMA2 BAR0 */ + S9B0, 32, /* SPI BAR0 */ + SAB0, 32, /* PWM1 BAR0 */ + SBB0, 32, /* PWM2 BAR0 */ + SCB0, 32, /* UART1 BAR0 */ + SDB0, 32, /* UART2 BAR0 */ + C0B0, 32, /* MMC BAR0 */ + C1B0, 32, /* SDIO BAR0 */ + C2B0, 32, /* SD Card BAR0 */ + LPB0, 32, /* LPE BAR0 */ -S0B1, 32, /* SDMA BAR1 */ -S1B1, 32, /* I2C1 BAR1 */ -S2B1, 32, /* I2C2 BAR1 */ -S3B1, 32, /* I2C3 BAR1 */ -S4B1, 32, /* I2C4 BAR1 */ -S5B1, 32, /* I2C5 BAR1 */ -S6B1, 32, /* I2C6 BAR1 */ -S7B1, 32, /* I2C7 BAR1 */ -S8B1, 32, /* SDMA2 BAR1 */ -S9B1, 32, /* SPI BAR1 */ -SAB1, 32, /* PWM1 BAR1 */ -SBB1, 32, /* PWM2 BAR1 */ -SCB1, 32, /* UART1 BAR1 */ -SDB1, 32, /* UART2 BAR1 */ -C0B1, 32, /* MMC BAR1 */ -C1B1, 32, /* SDIO BAR1 */ -C2B1, 32, /* SD Card BAR1 */ -LPB1, 32, /* LPE BAR1 */ + /* BAR 1 */ -/* Extra */ + S0B1, 32, /* SDMA BAR1 */ + S1B1, 32, /* I2C1 BAR1 */ + S2B1, 32, /* I2C2 BAR1 */ + S3B1, 32, /* I2C3 BAR1 */ + S4B1, 32, /* I2C4 BAR1 */ + S5B1, 32, /* I2C5 BAR1 */ + S6B1, 32, /* I2C6 BAR1 */ + S7B1, 32, /* I2C7 BAR1 */ + S8B1, 32, /* SDMA2 BAR1 */ + S9B1, 32, /* SPI BAR1 */ + SAB1, 32, /* PWM1 BAR1 */ + SBB1, 32, /* PWM2 BAR1 */ + SCB1, 32, /* UART1 BAR1 */ + SDB1, 32, /* UART2 BAR1 */ + C0B1, 32, /* MMC BAR1 */ + C1B1, 32, /* SDIO BAR1 */ + C2B1, 32, /* SD Card BAR1 */ + LPB1, 32, /* LPE BAR1 */ -LPFW, 32, /* LPE BAR2 Firmware */ + /* Extra */ + + LPFW, 32, /* LPE BAR2 Firmware */ +} diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index def3fc8f1f..293daa94a3 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -13,7 +13,7 @@ Name(\PICM, 0) /* IOAPIC/8259 */ External (NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -56,9 +56,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> - - Offset (0x1000), - #include <soc/intel/baytrail/acpi/device_nvs.asl> } /* Set flag to enable USB charging in S3 */ diff --git a/src/soc/intel/baytrail/acpi/platform.asl b/src/soc/intel/baytrail/acpi/platform.asl index 67b515ab86..143327684d 100644 --- a/src/soc/intel/baytrail/acpi/platform.asl +++ b/src/soc/intel/baytrail/acpi/platform.asl @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <soc/intel/baytrail/acpi/device_nvs.asl> #include <southbridge/intel/common/acpi/platform.asl> /* diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h index 6a5f1084a7..46fd9cc6ea 100644 --- a/src/soc/intel/baytrail/include/soc/device_nvs.h +++ b/src/soc/intel/baytrail/include/soc/device_nvs.h @@ -24,7 +24,7 @@ #define SCC_NVS_SDIO 1 #define SCC_NVS_SD 2 -typedef struct { +struct __packed device_nvs { /* Device Enabled in ACPI Mode */ u8 lpss_en[14]; u8 scc_en[3]; @@ -42,7 +42,6 @@ typedef struct { /* Extra */ u32 lpe_fw; /* LPE Firmware */ - u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ -} __packed device_nvs_t; +}; #endif diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 105d304f66..9fb0822b9b 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -4,7 +4,6 @@ #define _BAYTRAIL_NVS_H_ #include <stdint.h> -#include <soc/device_nvs.h> struct __packed global_nvs { /* Miscellaneous */ @@ -43,15 +42,6 @@ struct __packed global_nvs { u32 obsolete_cmem; /* 0x30 - CBMEM TOC */ u32 tolm; /* 0x34 - Top of Low Memory */ u32 cbmc; /* 0x38 - coreboot memconsole */ - u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */ - - u8 unused[76]; - - /* ChromeOS specific (0x100-0xfff) */ - u8 chromeos_reserve[0xf00]; - - /* Baytrail LPSS (0x1000) */ - device_nvs_t dev; }; #endif /* _BAYTRAIL_NVS_H_ */ diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 29633e57ee..a56ce5b6f0 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -12,7 +12,7 @@ #include <soc/iomap.h> #include <soc/iosf.h> #include <soc/lpc.h> -#include <soc/nvs.h> +#include <soc/device_nvs.h> #include <soc/pattrs.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -52,20 +52,15 @@ static void lpe_enable_acpi_mode(struct device *dev) REG_SCRIPT_END }; - struct global_nvs *gnvs; - - /* Find ACPI NVS to update BARs */ - gnvs = acpi_get_gnvs(); - if (!gnvs) - return; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); /* Save BAR0, BAR1, and firmware base to ACPI NVS */ - assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); - assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); - assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); + assign_device_nvs(dev, &dev_nvs->lpe_bar0, PCI_BASE_ADDRESS_0); + assign_device_nvs(dev, &dev_nvs->lpe_bar1, PCI_BASE_ADDRESS_1); + assign_device_nvs(dev, &dev_nvs->lpe_fw, FIRMWARE_PCI_REG_BASE); /* Device is enabled in ACPI mode */ - gnvs->dev.lpe_en = 1; + dev_nvs->lpe_en = 1; /* Put device in ACPI mode */ reg_script_run_on_dev(dev, ops); diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index afeb687be8..9f309b4c15 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -10,6 +10,7 @@ #include <soc/iosf.h> #include <soc/nvs.h> +#include <soc/device_nvs.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -28,24 +29,19 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index REG_SCRIPT_END }; struct resource *bar; - struct global_nvs *gnvs; - - /* Find ACPI NVS to update BARs */ - gnvs = acpi_get_gnvs(); - if (!gnvs) - return; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); /* Save BAR0 and BAR1 to ACPI NVS */ bar = find_resource(dev, PCI_BASE_ADDRESS_0); if (bar) - gnvs->dev.lpss_bar0[nvs_index] = (u32)bar->base; + dev_nvs->lpss_bar0[nvs_index] = (u32)bar->base; bar = find_resource(dev, PCI_BASE_ADDRESS_1); if (bar) - gnvs->dev.lpss_bar1[nvs_index] = (u32)bar->base; + dev_nvs->lpss_bar1[nvs_index] = (u32)bar->base; /* Device is enabled in ACPI mode */ - gnvs->dev.lpss_en[nvs_index] = 1; + dev_nvs->lpss_en[nvs_index] = 1; /* Put device in ACPI mode */ reg_script_run_on_dev(dev, ops); diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 8e3bd48ddd..a1e8eb7ca5 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -7,7 +7,7 @@ #include <reg_script.h> #include <soc/iosf.h> -#include <soc/nvs.h> +#include <soc/device_nvs.h> #include <soc/ramstage.h> static const struct reg_script scc_start_dll[] = { @@ -80,24 +80,19 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) REG_SCRIPT_END }; struct resource *bar; - struct global_nvs *gnvs; - - /* Find ACPI NVS to update BARs */ - gnvs = acpi_get_gnvs(); - if (!gnvs) - return; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); /* Save BAR0 and BAR1 to ACPI NVS */ bar = find_resource(dev, PCI_BASE_ADDRESS_0); if (bar) - gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base; + dev_nvs->scc_bar0[nvs_index] = (u32)bar->base; bar = find_resource(dev, PCI_BASE_ADDRESS_1); if (bar) - gnvs->dev.scc_bar1[nvs_index] = (u32)bar->base; + dev_nvs->scc_bar1[nvs_index] = (u32)bar->base; /* Device is enabled in ACPI mode */ - gnvs->dev.scc_en[nvs_index] = 1; + dev_nvs->scc_en[nvs_index] = 1; /* Put device in ACPI mode */ reg_script_run_on_dev(dev, ops); diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 41eeedae0b..e48ddbacab 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> +#include <acpi/acpi_gnvs.h> #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> @@ -17,6 +18,9 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/nvs.h> +#include <soc/device_nvs.h> + +#include <vendorcode/google/chromeos/gnvs.h> int southbridge_io_trap_handler(int smif) { @@ -204,6 +208,11 @@ static void southbridge_smi_gsmi(void) *ret = gsmi_exec(sub_command, param); } +void *acpi_get_device_nvs(void) +{ + return (u8 *)gnvs + GNVS_DEVICE_NVS_OFFSET; +} + /* * soc_legacy: A payload (Depthcharge) has indicated that the * legacy payload (SeaBIOS) is being loaded. Switch devices that are @@ -212,10 +221,11 @@ static void southbridge_smi_gsmi(void) */ static void soc_legacy(void) { + struct device_nvs *dev_nvs = acpi_get_device_nvs(); u32 reg32; /* LPE Device */ - if (gnvs->dev.lpe_en) { + if (dev_nvs->lpe_en) { reg32 = iosf_port58_read(LPE_PCICFGCTR1); reg32 &= ~(LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN); @@ -224,7 +234,7 @@ static void soc_legacy(void) /* SCC Devices */ #define SCC_ACPI_MODE_DISABLE(name_) \ - do { if (gnvs->dev.scc_en[SCC_NVS_ ## name_]) { \ + do { if (dev_nvs->scc_en[SCC_NVS_ ## name_]) { \ reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \ reg32 &= ~(SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); \ iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \ @@ -236,7 +246,7 @@ static void soc_legacy(void) /* LPSS Devices */ #define LPSS_ACPI_MODE_DISABLE(name_) \ - do { if (gnvs->dev.lpss_en[LPSS_NVS_ ## name_]) { \ + do { if (dev_nvs->lpss_en[LPSS_NVS_ ## name_]) { \ reg32 = iosf_lpss_read(LPSS_ ## name_ ## _CTL); \ reg32 &= ~LPSS_CTL_PCI_CFG_DIS | ~LPSS_CTL_ACPI_INT_EN; \ iosf_lpss_write(LPSS_ ## name_ ## _CTL, reg32); \ diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index dcc30ee567..001cab7960 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -8,6 +8,7 @@ if SOC_INTEL_BRASWELL config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_HAS_DEVICE_NVS select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl index 3722856331..aa0e9533f8 100644 --- a/src/soc/intel/braswell/acpi/device_nvs.asl +++ b/src/soc/intel/braswell/acpi/device_nvs.asl @@ -1,68 +1,74 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Device Enabled in ACPI Mode */ +External (NVSD) -S0EN, 8, /* SDMA Enable */ -S1EN, 8, /* I2C1 Enable */ -S2EN, 8, /* I2C2 Enable */ -S3EN, 8, /* I2C3 Enable */ -S4EN, 8, /* I2C4 Enable */ -S5EN, 8, /* I2C5 Enable */ -S6EN, 8, /* I2C6 Enable */ -S7EN, 8, /* I2C7 Enable */ -S8EN, 8, /* SDMA2 Enable */ -S9EN, 8, /* SPI Enable */ -SAEN, 8, /* PWM1 Enable */ -SBEN, 8, /* PWM2 Enable */ -SCEN, 8, /* UART2 Enable */ -SDEN, 8, /* UART2 Enable */ -C0EN, 8, /* MMC Enable */ -C1EN, 8, /* SDIO Enable */ -C2EN, 8, /* SD Card Enable */ -LPEN, 8, /* LPE Enable */ +OperationRegion (DNVS, SystemMemory, NVSD, 0x1000) +Field (DNVS, ByteAcc, NoLock, Preserve) +{ + /* Device Enabled in ACPI Mode */ -/* BAR 0 */ + S0EN, 8, /* SDMA Enable */ + S1EN, 8, /* I2C1 Enable */ + S2EN, 8, /* I2C2 Enable */ + S3EN, 8, /* I2C3 Enable */ + S4EN, 8, /* I2C4 Enable */ + S5EN, 8, /* I2C5 Enable */ + S6EN, 8, /* I2C6 Enable */ + S7EN, 8, /* I2C7 Enable */ + S8EN, 8, /* SDMA2 Enable */ + S9EN, 8, /* SPI Enable */ + SAEN, 8, /* PWM1 Enable */ + SBEN, 8, /* PWM2 Enable */ + SCEN, 8, /* UART2 Enable */ + SDEN, 8, /* UART2 Enable */ + C0EN, 8, /* MMC Enable */ + C1EN, 8, /* SDIO Enable */ + C2EN, 8, /* SD Card Enable */ + LPEN, 8, /* LPE Enable */ -S0B0, 32, /* SDMA BAR0 */ -S1B0, 32, /* I2C1 BAR0 */ -S2B0, 32, /* I2C2 BAR0 */ -S3B0, 32, /* I2C3 BAR0 */ -S4B0, 32, /* I2C4 BAR0 */ -S5B0, 32, /* I2C5 BAR0 */ -S6B0, 32, /* I2C6 BAR0 */ -S7B0, 32, /* I2C7 BAR0 */ -S8B0, 32, /* SDMA2 BAR0 */ -S9B0, 32, /* SPI BAR0 */ -SAB0, 32, /* PWM1 BAR0 */ -SBB0, 32, /* PWM2 BAR0 */ -SCB0, 32, /* UART1 BAR0 */ -SDB0, 32, /* UART2 BAR0 */ -C0B0, 32, /* MMC BAR0 */ -C1B0, 32, /* SDIO BAR0 */ -C2B0, 32, /* SD Card BAR0 */ -LPB0, 32, /* LPE BAR0 */ + /* BAR 0 */ -/* BAR 1 */ + S0B0, 32, /* SDMA BAR0 */ + S1B0, 32, /* I2C1 BAR0 */ + S2B0, 32, /* I2C2 BAR0 */ + S3B0, 32, /* I2C3 BAR0 */ + S4B0, 32, /* I2C4 BAR0 */ + S5B0, 32, /* I2C5 BAR0 */ + S6B0, 32, /* I2C6 BAR0 */ + S7B0, 32, /* I2C7 BAR0 */ + S8B0, 32, /* SDMA2 BAR0 */ + S9B0, 32, /* SPI BAR0 */ + SAB0, 32, /* PWM1 BAR0 */ + SBB0, 32, /* PWM2 BAR0 */ + SCB0, 32, /* UART1 BAR0 */ + SDB0, 32, /* UART2 BAR0 */ + C0B0, 32, /* MMC BAR0 */ + C1B0, 32, /* SDIO BAR0 */ + C2B0, 32, /* SD Card BAR0 */ + LPB0, 32, /* LPE BAR0 */ -S0B1, 32, /* SDMA BAR1 */ -S1B1, 32, /* I2C1 BAR1 */ -S2B1, 32, /* I2C2 BAR1 */ -S3B1, 32, /* I2C3 BAR1 */ -S4B1, 32, /* I2C4 BAR1 */ -S5B1, 32, /* I2C5 BAR1 */ -S6B1, 32, /* I2C6 BAR1 */ -S7B1, 32, /* I2C7 BAR1 */ -S8B1, 32, /* SDMA2 BAR1 */ -S9B1, 32, /* SPI BAR1 */ -SAB1, 32, /* PWM1 BAR1 */ -SBB1, 32, /* PWM2 BAR1 */ -SCB1, 32, /* UART1 BAR1 */ -SDB1, 32, /* UART2 BAR1 */ -C0B1, 32, /* MMC BAR1 */ -C1B1, 32, /* SDIO BAR1 */ -C2B1, 32, /* SD Card BAR1 */ -LPB1, 32, /* LPE BAR1 */ + /* BAR 1 */ -/* Extra */ + S0B1, 32, /* SDMA BAR1 */ + S1B1, 32, /* I2C1 BAR1 */ + S2B1, 32, /* I2C2 BAR1 */ + S3B1, 32, /* I2C3 BAR1 */ + S4B1, 32, /* I2C4 BAR1 */ + S5B1, 32, /* I2C5 BAR1 */ + S6B1, 32, /* I2C6 BAR1 */ + S7B1, 32, /* I2C7 BAR1 */ + S8B1, 32, /* SDMA2 BAR1 */ + S9B1, 32, /* SPI BAR1 */ + SAB1, 32, /* PWM1 BAR1 */ + SBB1, 32, /* PWM2 BAR1 */ + SCB1, 32, /* UART1 BAR1 */ + SDB1, 32, /* UART2 BAR1 */ + C0B1, 32, /* MMC BAR1 */ + C1B1, 32, /* SDIO BAR1 */ + C2B1, 32, /* SD Card BAR1 */ + LPB1, 32, /* LPE BAR1 */ -LPFW, 32, /* LPE BAR2 Firmware */ + /* Extra */ + + LPFW, 32, /* LPE BAR2 Firmware */ +} diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 564eb43788..6aa595713b 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -13,7 +13,7 @@ Name(\PICM, 0) /* IOAPIC/8259 */ External (NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -58,9 +58,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> - - Offset (0x1000), - #include <soc/intel/braswell/acpi/device_nvs.asl> } /* Set flag to enable USB charging in S3 */ diff --git a/src/soc/intel/braswell/acpi/platform.asl b/src/soc/intel/braswell/acpi/platform.asl index 7fd3984e40..6a01c28e9c 100644 --- a/src/soc/intel/braswell/acpi/platform.asl +++ b/src/soc/intel/braswell/acpi/platform.asl @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <soc/intel/braswell/acpi/device_nvs.asl> + /* Enable ACPI _SWS methods */ #include <soc/intel/common/acpi/acpi_wake_source.asl> #include <southbridge/intel/common/acpi/platform.asl> - /* * The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h index 73af09ad41..bf8974d840 100644 --- a/src/soc/intel/braswell/include/soc/device_nvs.h +++ b/src/soc/intel/braswell/include/soc/device_nvs.h @@ -24,7 +24,7 @@ #define SCC_NVS_SDIO 1 #define SCC_NVS_SD 2 -typedef struct { +struct __packed device_nvs { /* Device Enabled in ACPI Mode */ u8 lpss_en[14]; u8 scc_en[3]; @@ -42,6 +42,6 @@ typedef struct { /* Extra */ u32 lpe_fw; /* LPE Firmware */ -} __packed device_nvs_t; +}; #endif /* _SOC_DEVICE_NVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 41bb5a1a54..7d27c3f822 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -4,7 +4,6 @@ #define _SOC_NVS_H_ #include <stdint.h> -#include <soc/device_nvs.h> struct __packed global_nvs { /* Miscellaneous */ @@ -45,15 +44,6 @@ struct __packed global_nvs { u32 obsolete_cmem; /* 0x30 - CBMEM TOC */ u32 tolm; /* 0x34 - Top of Low Memory */ u32 cbmc; /* 0x38 - coreboot memconsole */ - u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */ - - u8 unused[76]; - - /* ChromeOS specific (0x100-0xfff) */ - u8 chromeos_reserve[0xf00]; - - /* LPSS (0x1000) */ - device_nvs_t dev; }; #endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 14be808136..59cabee707 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -12,7 +12,7 @@ #include <soc/iomap.h> #include <soc/iosf.h> #include <soc/lpc.h> -#include <soc/nvs.h> +#include <soc/device_nvs.h> #include <soc/pattrs.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -53,20 +53,15 @@ static void lpe_enable_acpi_mode(struct device *dev) REG_SCRIPT_END }; - struct global_nvs *gnvs; - - /* Find ACPI NVS to update BARs */ - gnvs = acpi_get_gnvs(); - if (!gnvs) - return; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); /* Save BAR0, BAR1, and firmware base to ACPI NVS */ - assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); - assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_2); - assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); + assign_device_nvs(dev, &dev_nvs->lpe_bar0, PCI_BASE_ADDRESS_0); + assign_device_nvs(dev, &dev_nvs->lpe_bar1, PCI_BASE_ADDRESS_2); + assign_device_nvs(dev, &dev_nvs->lpe_fw, FIRMWARE_PCI_REG_BASE); /* Device is enabled in ACPI mode */ - gnvs->dev.lpe_en = 1; + dev_nvs->lpe_en = 1; /* Put device in ACPI mode */ reg_script_run_on_dev(dev, ops); diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index 961d405156..93ee3da273 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -9,7 +9,7 @@ #include <reg_script.h> #include <soc/iosf.h> -#include <soc/nvs.h> +#include <soc/device_nvs.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -28,24 +28,19 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index REG_SCRIPT_END }; struct resource *bar; - struct global_nvs *gnvs; - - /* Find ACPI NVS to update BARs */ - gnvs = acpi_get_gnvs(); - if (!gnvs) - return; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); /* Save BAR0 and BAR1 to ACPI NVS */ bar = find_resource(dev, PCI_BASE_ADDRESS_0); if (bar) - gnvs->dev.lpss_bar0[nvs_index] = (u32)bar->base; + dev_nvs->lpss_bar0[nvs_index] = (u32)bar->base; bar = find_resource(dev, PCI_BASE_ADDRESS_1); if (bar) - gnvs->dev.lpss_bar1[nvs_index] = (u32)bar->base; + dev_nvs->lpss_bar1[nvs_index] = (u32)bar->base; /* Device is enabled in ACPI mode */ - gnvs->dev.lpss_en[nvs_index] = 1; + dev_nvs->lpss_en[nvs_index] = 1; /* Put device in ACPI mode */ reg_script_run_on_dev(dev, ops); diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index 45ce8de982..c6d4f5201e 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -5,27 +5,22 @@ #include <device/device.h> #include <device/pci.h> #include <soc/iosf.h> -#include <soc/nvs.h> +#include <soc/device_nvs.h> #include <soc/ramstage.h> void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct resource *bar; - struct global_nvs *gnvs; - - /* Find ACPI NVS to update BARs */ - gnvs = acpi_get_gnvs(); - if (!gnvs) - return; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); /* Save BAR0 and BAR1 to ACPI NVS */ bar = find_resource(dev, PCI_BASE_ADDRESS_0); if (bar) - gnvs->dev.scc_bar0[nvs_index] = bar->base; + dev_nvs->scc_bar0[nvs_index] = bar->base; bar = find_resource(dev, PCI_BASE_ADDRESS_2); if (bar) - gnvs->dev.scc_bar1[nvs_index] = bar->base; + dev_nvs->scc_bar1[nvs_index] = bar->base; /* Device is enabled in ACPI mode */ - gnvs->dev.scc_en[nvs_index] = 1; + dev_nvs->scc_en[nvs_index] = 1; } diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 14bbb813ba..06621f159f 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -11,6 +11,7 @@ config INTEL_LYNXPOINT_LP config SOC_SPECIFIC_OPTIONS def_bool y + select ACPI_HAS_DEVICE_NVS select ACPI_INTEL_HARDWARE_SLEEP_VALUES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/soc/intel/broadwell/acpi/device_nvs.asl new file mode 100644 index 0000000000..30bb5b5cd0 --- /dev/null +++ b/src/soc/intel/broadwell/acpi/device_nvs.asl @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +External (NVSD) + +OperationRegion (DNVS, SystemMemory, NVSD, 0x1000) +Field (DNVS, ByteAcc, NoLock, Preserve) +{ + /* Device enables in ACPI mode */ + + S0EN, 8, // DMA Enable + S1EN, 8, // I2C0 Enable + S2EN, 8, // I2C1 Enable + S3EN, 8, // SPI0 Enable + S4EN, 8, // SPI1 Enable + S5EN, 8, // UART0 Enable + S6EN, 8, // UART1 Enable + S7EN, 8, // SDIO Enable + S8EN, 8, // ADSP Enable + + /* BAR 0 */ + + S0B0, 32, // DMA BAR0 + S1B0, 32, // I2C0 BAR0 + S2B0, 32, // I2C1 BAR0 + S3B0, 32, // SPI0 BAR0 + S4B0, 32, // SPI1 BAR0 + S5B0, 32, // UART0 BAR0 + S6B0, 32, // UART1 BAR0 + S7B0, 32, // SDIO BAR0 + S8B0, 32, // ADSP BAR0 + + /* BAR 1 */ + + S0B1, 32, // DMA BAR1 + S1B1, 32, // I2C0 BAR1 + S2B1, 32, // I2C1 BAR1 + S3B1, 32, // SPI0 BAR1 + S4B1, 32, // SPI1 BAR1 + S5B1, 32, // UART0 BAR1 + S6B1, 32, // UART1 BAR1 + S7B1, 32, // SDIO BAR1 + S8B1, 32, // ADSP BAR1 +} diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/soc/intel/broadwell/acpi/platform.asl index 880b2061ec..fe254ff6f0 100644 --- a/src/soc/intel/broadwell/acpi/platform.asl +++ b/src/soc/intel/broadwell/acpi/platform.asl @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <soc/intel/broadwell/acpi/device_nvs.asl> #include <southbridge/intel/common/acpi/platform.asl> /* diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h index 2b784557cd..27304b573d 100644 --- a/src/soc/intel/broadwell/include/soc/device_nvs.h +++ b/src/soc/intel/broadwell/include/soc/device_nvs.h @@ -15,10 +15,10 @@ #define SIO_NVS_SDIO 7 #define SIO_NVS_ADSP 8 -typedef struct { +struct __packed device_nvs { u8 enable[9]; u32 bar0[9]; u32 bar1[9]; -} __packed device_nvs_t; +}; #endif diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h index 1b6a231651..70f26e8ef1 100644 --- a/src/soc/intel/broadwell/include/soc/nvs.h +++ b/src/soc/intel/broadwell/include/soc/nvs.h @@ -4,7 +4,6 @@ #define _BROADWELL_NVS_H_ #include <stdint.h> -#include <soc/device_nvs.h> struct __packed global_nvs { /* Miscellaneous */ @@ -35,15 +34,6 @@ struct __packed global_nvs { u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ - u8 unused1[132]; /* 0x30 - 0xb3 - unused */ - - u8 unused2[76]; - - /* ChromeOS specific (0x100 - 0xfff) */ - u8 chromeos_reserve[0xf00]; - - /* Device specific (0x1000) */ - device_nvs_t dev; }; #endif diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl index b83b957c6c..88fe4b1218 100644 --- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl @@ -12,7 +12,7 @@ Name (\PICM, 0) // IOAPIC/8259 */ External (NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -47,40 +47,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> - - Offset (0x1000), - /* Device enables in ACPI mode */ - S0EN, 8, // DMA Enable - S1EN, 8, // I2C0 Enable - S2EN, 8, // I2C1 Enable - S3EN, 8, // SPI0 Enable - S4EN, 8, // SPI1 Enable - S5EN, 8, // UART0 Enable - S6EN, 8, // UART1 Enable - S7EN, 8, // SDIO Enable - S8EN, 8, // ADSP Enable - - /* BAR 0 */ - S0B0, 32, // DMA BAR0 - S1B0, 32, // I2C0 BAR0 - S2B0, 32, // I2C1 BAR0 - S3B0, 32, // SPI0 BAR0 - S4B0, 32, // SPI1 BAR0 - S5B0, 32, // UART0 BAR0 - S6B0, 32, // UART1 BAR0 - S7B0, 32, // SDIO BAR0 - S8B0, 32, // ADSP BAR0 - - /* BAR 1 */ - S0B1, 32, // DMA BAR1 - S1B1, 32, // I2C0 BAR1 - S2B1, 32, // I2C1 BAR1 - S3B1, 32, // SPI0 BAR1 - S4B1, 32, // SPI1 BAR1 - S5B1, 32, // UART0 BAR1 - S6B1, 32, // UART1 BAR1 - S7B1, 32, // SDIO BAR1 - S8B1, 32, // ADSP BAR1 } /* Set flag to enable USB charging in S3 */ diff --git a/src/soc/intel/broadwell/pch/adsp.c b/src/soc/intel/broadwell/pch/adsp.c index 06dd38bd8a..a65ff4b469 100644 --- a/src/soc/intel/broadwell/pch/adsp.c +++ b/src/soc/intel/broadwell/pch/adsp.c @@ -10,7 +10,7 @@ #include <soc/adsp.h> #include <soc/device_nvs.h> #include <soc/iobp.h> -#include <soc/nvs.h> +#include <soc/device_nvs.h> #include <soc/pch.h> #include <soc/ramstage.h> #include <soc/rcba.h> @@ -79,20 +79,15 @@ static void adsp_init(struct device *dev) pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE); if (config->sio_acpi_mode) { - /* Configure for ACPI mode */ - struct global_nvs *gnvs; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); + /* Configure for ACPI mode */ printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n"); - /* Find ACPI NVS to update BARs */ - gnvs = acpi_get_gnvs(); - if (!gnvs) - return; - /* Save BAR0 and BAR1 to ACPI NVS */ - gnvs->dev.bar0[SIO_NVS_ADSP] = (u32)bar0->base; - gnvs->dev.bar1[SIO_NVS_ADSP] = (u32)bar1->base; - gnvs->dev.enable[SIO_NVS_ADSP] = 1; + dev_nvs->bar0[SIO_NVS_ADSP] = (u32)bar0->base; + dev_nvs->bar1[SIO_NVS_ADSP] = (u32)bar1->base; + dev_nvs->enable[SIO_NVS_ADSP] = 1; /* Set PCI Config Disable Bit */ pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~0, ADSP_PCICFGCTL_PCICD); diff --git a/src/soc/intel/broadwell/pch/serialio.c b/src/soc/intel/broadwell/pch/serialio.c index d32a27ddca..28f34b7d53 100644 --- a/src/soc/intel/broadwell/pch/serialio.c +++ b/src/soc/intel/broadwell/pch/serialio.c @@ -8,7 +8,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <soc/iobp.h> -#include <soc/nvs.h> +#include <soc/device_nvs.h> #include <soc/pci_devs.h> #include <soc/pch.h> #include <soc/ramstage.h> @@ -233,20 +233,15 @@ static void serialio_init(struct device *dev) } if (config->sio_acpi_mode) { - struct global_nvs *gnvs; - - /* Find ACPI NVS to update BARs */ - gnvs = acpi_get_gnvs(); - if (!gnvs) - return; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); /* Save BAR0 and BAR1 to ACPI NVS */ - gnvs->dev.bar0[sio_index] = (u32)bar0->base; - gnvs->dev.bar1[sio_index] = (u32)bar1->base; + dev_nvs->bar0[sio_index] = (u32)bar0->base; + dev_nvs->bar1[sio_index] = (u32)bar1->base; /* Do not enable UART if it is used as debug port */ if (!serialio_uart_is_debug(dev)) - gnvs->dev.enable[sio_index] = 1; + dev_nvs->enable[sio_index] = 1; /* Put device in D3hot state via BAR1 */ if (dev->path.pci.devfn != PCH_DEVFN_SDMA) |