diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-02 22:23:11 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-09-04 15:09:32 +0000 |
| commit | 439356fabcacbbc3a3231f6e27b5298f8f5ad41f (patch) | |
| tree | 82e94a01f5a59b1d495db0e6225556bbbd0edfb0 /src/soc/intel | |
| parent | bc98cc66b2fe787173ec04b84ea11bc3e57fe373 (diff) | |
x86: remove cpu_incs as romstage Make variable
When building up which files to include in romstage there
were both 'cpu_incs' and 'cpu_incs-y' which were used to
generate crt0.S. Remove the former to settle on cpu_incs-y
as the way to be included.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi. No include file changes.
Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/baytrail/romstage/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/Makefile.inc | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index 345037d51f..5086a4e047 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,7 +1,7 @@ -cpu_incs += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc +cpu_incs-y += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc romstage-y += romstage.c romstage-y += raminit.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c romstage-y += gfx.c romstage-y += pmc.c -romstage-y += early_spi.c
\ No newline at end of file +romstage-y += early_spi.c diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index ae0f9806fd..161781285c 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,4 +1,4 @@ -cpu_incs += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc +cpu_incs-y += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc romstage-y += cpu.c romstage-y += pch.c |