diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 22:32:28 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-19 20:15:15 +0200 |
| commit | 27928685198ab911452a3d5f789fec90a575ad05 (patch) | |
| tree | 87ee896367ebb3c2e2ace63915023e2dcd55bbb9 /src/soc/intel | |
| parent | a3a06aeac5879f36f35bb462616e29fbe4a177f9 (diff) | |
drivers/intel/fsp2_0: set BootLoaderTolumSize generically
The amount of reserved memory just below the DRAM limit in
32-bit space is defined in the FSP 2.0 specification within
the FSPM_ARCH_UPD structure. There's no need to make the
chipset code set the same value as needed for coreboot.
The chipset code can always change the value if it needs
after the common setting being applied.
Remove the call in soc/intel/apollolake as it's no longer
needed.
BUG=chrome-os-partner:52679
Change-Id: I69a1fee7a7b53c109afd8ee0f03cb8506584d571
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15738
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1a860e8eb2..ddbfaa4b39 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -213,8 +213,6 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) /* Do NOT let FSP do any GPIO pad configuration */ mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL; - /* Reserve enough memory under TOLUD to save CBMEM header */ - mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); /* * FSPM_UPD passed here is populated with default values provided by * the blob itself. We let FSPM use top of CAR region of the size it |