src/soc: Capitalize CPU, ACPI, RAM and ROM

Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15963
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>

20 files changed, 27 insertions, 27 deletions

diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl
index f2a7e76f20..030d3ebaec 100644
--- a/src/soc/intel/apollolake/acpi/gpio.asl
+++ b/src/soc/intel/apollolake/acpi/gpio.asl
@@ -146,8 +146,8 @@ scope (\_SB) {
 Scope(\_GPE)
 {
 	/* Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads
-	 * _L0F in scope GPE it sets bit for gpio_tier1_sci_en in acpi enable
-	 * register at 0x430. For APL acpi enable register DW0 i.e., ACPI
+	 * _L0F in scope GPE it sets bit for gpio_tier1_sci_en in ACPI enable
+	 * register at 0x430. For APL ACPI enable register DW0 i.e., ACPI
 	 * GPE0a_EN at 0x430 is reserved.
 	 */
 	Method(_L0F, 0) {}
diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h
index 3ad2110ded..436cc33477 100644
--- a/src/soc/intel/baytrail/include/soc/iosf.h
+++ b/src/soc/intel/baytrail/include/soc/iosf.h
@@ -185,11 +185,11 @@ void iosf_ssus_write(int reg, uint32_t val);
 #define BNOCACHE		0x23
 /* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */
 #define BUNIT_BMBOUND		0x25
-/* BMBOUND_HI describes the available ram above 4GiB. It has a
+/* BMBOUND_HI describes the available RAM above 4GiB. It has a
  * 256MiB granularity. Physical address bits 35:28 are compared with 31:24
  * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB
  * granularity care needs to be taken with the e820 map to account for a hole
- * in the ram. */
+ * in the RAM. */
 #define BUNIT_BMBOUND_HI	0x26
 #define BUNIT_MMCONF_REG	0x27
 /* The SMMRR registers define the SMM region in MiB granularity. */
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 96ae86dd63..2b5174435b 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -305,7 +305,7 @@ static void *setup_stack_and_mttrs(void)
 	num_mtrrs++;
 
 	top_of_ram = (uint32_t)cbmem_top();
-	/* Cache 8MiB below the top of ram. The top of ram under 4GiB is the
+	/* Cache 8MiB below the top of ram. The top of RAM under 4GiB is the
 	 * start of the TSEG region. It is required to be 8MiB aligned. Set
 	 * this area as cacheable so it can be used later for ramstage before
 	 * setting up the entire RAM as cacheable. */
@@ -315,7 +315,7 @@ static void *setup_stack_and_mttrs(void)
 	slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
 	num_mtrrs++;
 
-	/* Cache 8MiB at the top of ram. Top of ram is where the TSEG
+	/* Cache 8MiB at the top of ram. Top of RAM is where the TSEG
 	 * region resides. However, it is not restricted to SMM mode until
 	 * SMM has been relocated. By setting the region to cacheable it
 	 * provides faster access when relocating the SMM handler as well
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 7fa4b790fd..4dca11019e 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -100,7 +100,7 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE
 	default 0x800
 	help
 	  The amount of anticipated stack usage from the data cache
-	  during pre-ram rom stage execution.
+	  during pre-ram ROM stage execution.
 
 config RESET_ON_INVALID_RAMSTAGE_CACHE
 	bool "Reset the system on S3 wake when ramstage cache invalid."
diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h
index 5afca3e123..c0b3f06cc2 100644
--- a/src/soc/intel/braswell/include/soc/iosf.h
+++ b/src/soc/intel/braswell/include/soc/iosf.h
@@ -122,11 +122,11 @@ void reg_script_write_iosf(struct reg_script_context *ctx);
 /* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */
 #define BUNIT_BMBOUND		0x25
 /*
- * BMBOUND_HI describes the available ram above 4GiB. It has a
+ * BMBOUND_HI describes the available RAM above 4GiB. It has a
  * 256MiB granularity. Physical address bits 35:28 are compared with 31:24
  * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB
  * granularity care needs to be taken with the e820 map to account for a hole
- * in the ram.
+ * in the RAM.
  */
 #define BUNIT_BMBOUND_HI	0x26
 #define BUNIT_MMCONF_REG	0x27
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 545eb62058..2d6176af6b 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -109,7 +109,7 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE
 	default 0x2000
 	help
 	  The amount of anticipated stack usage from the data cache
-	  during pre-ram rom stage execution.
+	  during pre-ram ROM stage execution.
 
 config HAVE_MRC
 	bool "Add a Memory Reference Code binary"
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 2afdfadc3e..16f350c993 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -576,7 +576,7 @@ static void cpu_core_init(device_t cpu)
 	/* Clear out pending MCEs */
 	configure_mca();
 
-	/* Enable the local cpu apics */
+	/* Enable the local CPU apics */
 	enable_lapic_tpr();
 	setup_lapic();
 
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index 37d7f30a68..24720d14a3 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -147,7 +147,7 @@ clear_mtrrs:
 	wrmsr
 
 	post_code(0x27)
-	/* Enable caching for ram init code to run faster */
+	/* Enable caching for RAM init code to run faster */
 	movl	$MTRR_PHYS_BASE(2), %ecx
 	movl	$(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
 	xorl	%edx, %edx
diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c
index 76307cfbb5..86a1c02b15 100644
--- a/src/soc/intel/broadwell/romstage/stack.c
+++ b/src/soc/intel/broadwell/romstage/stack.c
@@ -78,7 +78,7 @@ void *setup_stack_and_mttrs(void)
 	num_mtrrs++;
 
 	top_of_ram = (uint32_t)cbmem_top();
-	/* Cache 8MiB below the top of ram. The top of ram under 4GiB is the
+	/* Cache 8MiB below the top of ram. The top of RAM under 4GiB is the
 	 * start of the TSEG region. It is required to be 8MiB aligned. Set
 	 * this area as cacheable so it can be used later for ramstage before
 	 * setting up the entire RAM as cacheable. */
@@ -88,7 +88,7 @@ void *setup_stack_and_mttrs(void)
 	slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
 	num_mtrrs++;
 
-	/* Cache 8MiB at the top of ram. Top of ram is where the TSEG
+	/* Cache 8MiB at the top of ram. Top of RAM is where the TSEG
 	 * region resides. However, it is not restricted to SMM mode until
 	 * SMM has been relocated. By setting the region to cacheable it
 	 * provides faster access when relocating the SMM handler as well
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index 6fd609b508..873e909c85 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -136,7 +136,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 	msr_t mtrr_cap;
 	struct smm_relocation_params *relo_params = &smm_reloc_params;
 
-	printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
+	printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu);
 
 	/* Determine if the processor supports saving state in MSRs. If so,
 	 * enable it before the non-BSPs run so that SMM relocation can occur
diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c
index 03c63575d0..dc59ab7756 100644
--- a/src/soc/intel/broadwell/stage_cache.c
+++ b/src/soc/intel/broadwell/stage_cache.c
@@ -21,7 +21,7 @@
 void stage_cache_external_region(void **base, size_t *size)
 {
 	/* The ramstage cache lives in the TSEG region.
-	 * The top of ram is defined to be the TSEG base address. */
+	 * The top of RAM is defined to be the TSEG base address. */
 	u32 offset = smm_region_size();
 	offset -= CONFIG_IED_REGION_SIZE;
 	offset -= CONFIG_SMM_RESERVED_SIZE;
diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h
index 63566db6c8..845e0f0ae4 100644
--- a/src/soc/intel/common/acpi.h
+++ b/src/soc/intel/common/acpi.h
@@ -85,7 +85,7 @@ acpi_cstate_t *soc_get_cstate_map(int *num_entries);
 acpi_tstate_t *soc_get_tss_table(int *num_entries);
 
 /*
- * soc_get_acpi_base_address returns the acpi base address for the SOC
+ * soc_get_acpi_base_address returns the ACPI base address for the SOC
  */
 uint16_t soc_get_acpi_base_address(void);
 
diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h
index 6b64690674..c019286065 100644
--- a/src/soc/intel/common/gma.h
+++ b/src/soc/intel/common/gma.h
@@ -53,7 +53,7 @@ typedef struct {
 
 #define SBIOS_VERSION_SIZE 32
 
-/* mailbox 1: public acpi methods */
+/* mailbox 1: public ACPI methods */
 typedef struct {
 	u32	drdy;
 	u32	csts;
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index 3fba0b7808..742b2ef794 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -94,7 +94,7 @@ static void pre_mp_init(void)
 {
 	x86_mtrr_check();
 
-	/* Enable the local cpu apics */
+	/* Enable the local CPU apics */
 	setup_lapic();
 }
 
diff --git a/src/soc/intel/fsp_baytrail/include/soc/iosf.h b/src/soc/intel/fsp_baytrail/include/soc/iosf.h
index a220469cd2..0982da68db 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/iosf.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/iosf.h
@@ -186,11 +186,11 @@ void iosf_ssus_write(int reg, uint32_t val);
 #define BNOCACHE		0x23
 /* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */
 #define BUNIT_BMBOUND		0x25
-/* BMBOUND_HI describes the available ram above 4GiB. It has a
+/* BMBOUND_HI describes the available RAM above 4GiB. It has a
  * 256MiB granularity. Physical address bits 35:28 are compared with 31:24
  * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB
  * granularity care needs to be taken with the e820 map to account for a hole
- * in the ram. */
+ * in the RAM. */
 #define BUNIT_BMBOUND_HI	0x26
 #define BUNIT_MMCONF_REG	0x27
 /* The SMMRR registers define the SMM region in MiB granularity. */
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index 881ad0b9b5..a7ed414da8 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -244,7 +244,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
 	late_mainboard_romstage_entry();
 	post_code(0x4c);
 
-	/* if S3 resume skip ram check */
+	/* if S3 resume skip RAM check */
 	if (prev_sleep_state != ACPI_S3) {
 		quick_ram_check();
 		post_code(0x4d);
diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c
index ca082041e9..1e4ec34858 100644
--- a/src/soc/intel/fsp_broadwell_de/cpu.c
+++ b/src/soc/intel/fsp_broadwell_de/cpu.c
@@ -31,7 +31,7 @@ static void pre_mp_init(void)
 {
 	x86_mtrr_check();
 
-	/* Enable the local cpu apics */
+	/* Enable the local CPU apics */
 	setup_lapic();
 }
 
diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c
index a770c81bf1..eb8c46ecf2 100644
--- a/src/soc/intel/quark/tsc_freq.c
+++ b/src/soc/intel/quark/tsc_freq.c
@@ -20,7 +20,7 @@
 
 static unsigned long bus_freq_khz(void)
 {
-	/* cpu freq = 400 MHz */
+	/* CPU freq = 400 MHz */
 	return 400 * 1000;
 }
 
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index b7353cab6b..2b75e5aeb4 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -352,7 +352,7 @@ static void cpu_core_init(device_t cpu)
 	/* Clear out pending MCEs */
 	configure_mca();
 
-	/* Enable the local cpu apics */
+	/* Enable the local CPU apics */
 	enable_lapic_tpr();
 	setup_lapic();
 
@@ -487,7 +487,7 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
 	 * 0x08b with the Patch revision id one less than the id in the
 	 * microcode binary. The PRMRR support is indicated in the MSR
 	 * MTRRCAP[12]. Check for this feature and avoid reloading the
-	 * same microcode during cpu initialization.
+	 * same microcode during CPU initialization.
 	 */
 	msr = rdmsr(MTRR_CAP_MSR);
 	return (msr.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1);
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index 807aaa38ac..1cc8e54e55 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -138,7 +138,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 	msr_t mtrr_cap;
 	struct smm_relocation_params *relo_params = &smm_reloc_params;
 
-	printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
+	printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu);
 
 	/*
 	 * Determine if the processor supports saving state in MSRs. If so,