diff options
| author | Philipp Deppenwiese <zaolin@das-labor.org> | 2018-02-27 19:40:52 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-06-04 20:33:07 +0000 |
| commit | c07f8fbe6fd13e4245da71574b52b47e9733db84 (patch) | |
| tree | 12db8b3c40552eab81045c6165538e2d3ba36ce8 /src/soc/intel | |
| parent | 961d31bdb3c97e177156ed335d6f2c726d08ab51 (diff) | |
security/tpm: Unify the coreboot TPM software stack
* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/braswell/romstage/romstage.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/common/Makefile.inc | 8 |
5 files changed, 12 insertions, 14 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 5df5ed1b56..371d0c4cb6 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -124,7 +124,7 @@ config VBOOT config TPM_ON_FAST_SPI bool default n - select LPC_TPM + depends on MAINBOARD_HAS_LPC_TPM help TPM part is conntected on Fast SPI interface, but the LPC MMIO TPM transactions are decoded and serialized over the SPI interface. diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 980064c2b0..e38957eaf0 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -30,7 +30,7 @@ #include <stage_cache.h> #include <string.h> #include <timestamp.h> -#include <security/tpm/tis.h> +#include <security/tpm/tspi.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -229,9 +229,8 @@ void romstage_common(struct romstage_params *params) romstage_handoff_init(prev_sleep_state == ACPI_S3); - if (IS_ENABLED(CONFIG_LPC_TPM)) { - init_tpm(prev_sleep_state == ACPI_S3); - } + if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) + tpm_setup(prev_sleep_state == ACPI_S3); } void asmlinkage romstage_after_car(void) diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 7cedf90331..2fbe406fef 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -43,7 +43,7 @@ #include <soc/romstage.h> #include <soc/smm.h> #include <soc/spi.h> -#include <security/tpm/tis.h> +#include <security/tpm/tspi.h> void program_base_addresses(void) { diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 8a3f2911a0..1e2aa22271 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -26,7 +26,7 @@ #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <elog.h> -#include <security/tpm/tis.h> +#include <security/tpm/tspi.h> #include <program_loading.h> #include <romstage_handoff.h> #include <stage_cache.h> @@ -111,9 +111,8 @@ void romstage_common(struct romstage_params *params) romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3); -#if IS_ENABLED(CONFIG_LPC_TPM) - init_tpm(params->power_state->prev_sleep_state == ACPI_S3); -#endif + if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) + tpm_setup(params->power_state->prev_sleep_state == ACPI_S3); } asmlinkage void romstage_after_car(void) diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index bfd6a77703..def7d24c06 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -25,10 +25,10 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c -bootblock-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c -verstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c -romstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c -ramstage-$(CONFIG_MAINBOARD_HAS_TPM_CR50) += tpm_tis.c +bootblock-$(CONFIG_TPM_CR50) += tpm_tis.c +verstage-$(CONFIG_TPM_CR50) += tpm_tis.c +romstage-$(CONFIG_TPM_CR50) += tpm_tis.c +ramstage-$(CONFIG_TPM_CR50) += tpm_tis.c ifeq ($(CONFIG_MMA),y) MMA_BLOBS_PATH = $(call strip_quotes,$(CONFIG_MMA_BLOBS_PATH)) |