diff options
| author | Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> | 2020-05-27 14:20:21 -0700 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-05-31 09:37:00 +0000 |
| commit | 03a05b47e06392e028dbdb73900219d45084b2fd (patch) | |
| tree | 941046b1cdfac0640e4fd88aba47686fc358ace4 /src/soc/intel | |
| parent | 5694342a8136e85fe474c09e425d0476d9fc4d2b (diff) | |
soc/intel/tigerlake/acpi: Update camera_clock_ctl.asl to ASL2.0
This change updates camera_clock_ctl.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
BUG=none
BRANCH=none
TEST="BUILD for volteer"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: I6370e4b268331bfba5bc0392f27c560836b6ea72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl index 3d31502526..f9f48bf04a 100644 --- a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl +++ b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl @@ -11,8 +11,7 @@ Scope (\_SB.PCI0) { /* IsCLK PCH base register for clock settings */ Name (ICKB, 0) - Store (PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, ICKB) - + ICKB = PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1 /* * Arg0 : Clock Number * Return : Offset of register to control the clock in Arg0 |