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authorSean Rhodes <sean@starlabs.systems>2023-02-27 13:08:50 +0000
committerFelix Held <felix-coreboot@felixheld.de>2023-03-01 14:25:38 +0000
commitfd4ad29f1824ad5d8df67f3e30d3908d24cbd8a4 (patch)
tree33da5d54d2281c707500049e86cabfff7e4d5077 /src/soc/intel
parentfd51af6286d939a8308ff65260f0fa7ac948507d (diff)
soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol
Replace the SOC_INTEL_TIGERLAKE_S3 and SOC_INTEL_ALDERLAKE_S3 with the D3COLD_SUPPORT symbol, as it allows for more granular control. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I07e8c84e5ad8f390bfbac017dd23736e7a6ced9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/alderlake/Kconfig6
-rw-r--r--src/soc/intel/alderlake/acpi/tcss.asl4
-rw-r--r--src/soc/intel/alderlake/acpi/tcss_dma.asl12
-rw-r--r--src/soc/intel/alderlake/acpi/tcss_pcierp.asl12
-rw-r--r--src/soc/intel/alderlake/acpi/tcss_xhci.asl8
-rw-r--r--src/soc/intel/tigerlake/Kconfig6
-rw-r--r--src/soc/intel/tigerlake/acpi/tcss.asl4
-rw-r--r--src/soc/intel/tigerlake/acpi/tcss_dma.asl12
-rw-r--r--src/soc/intel/tigerlake/acpi/tcss_pcierp.asl10
-rw-r--r--src/soc/intel/tigerlake/acpi/tcss_xhci.asl8
10 files changed, 35 insertions, 47 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index dd6bb22952..a8c9aebe27 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -328,12 +328,6 @@ config SOC_INTEL_I2C_DEV_MAX
int
default 8
-config SOC_INTEL_ALDERLAKE_S3
- bool
- default n
- help
- Select if using S3 instead of S0ix to disable D3Cold.
-
config ENABLE_SATA_TEST_MODE
bool "Enable test mode for SATA margining"
default n
diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl
index 1f626fc7d3..5c95997f57 100644
--- a/src/soc/intel/alderlake/acpi/tcss.asl
+++ b/src/soc/intel/alderlake/acpi/tcss.asl
@@ -583,7 +583,7 @@ Scope (\_SB.PCI0)
}
}
-#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
Method (TCON, 0)
{
/* Reset IOM D3 cold bit if it is in D3 cold now. */
@@ -654,7 +654,7 @@ Scope (\_SB.PCI0)
STAT = 0
}
}
-#endif // SOC_INTEL_ALDERLAKE_S3
+#endif // D3COLD_SUPPORT
/*
* TCSS xHCI device
diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl
index 1483c0b5ac..ca47bd0ec9 100644
--- a/src/soc/intel/alderlake/acpi/tcss_dma.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl
@@ -28,16 +28,16 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
Method (_S0W, 0x0)
{
-#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
Return (0x04)
#else
Return (0x03)
-#endif // SOC_INTEL_ALDERLAKE_S3
+#endif // D3COLD_SUPPORT
}
Method (_PR0)
{
-#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -49,12 +49,12 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // SOC_INTEL_ALDERLAKE_S3
+#endif // D3COLD_SUPPORT
}
Method (_PR3)
{
-#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -66,7 +66,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // SOC_INTEL_ALDERLAKE_S3
+#endif // D3COLD_SUPPORT
}
/*
diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
index 4f1eec5d2c..6dbde46f49 100644
--- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl
@@ -247,16 +247,16 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
-#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
Return (0x4)
#else
Return (0x3)
-#endif // SOC_INTEL_ALDERLAKE_S3
+#endif // D3COLD_SUPPORT
}
Method (_PR0)
{
-#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -268,12 +268,12 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // SOC_INTEL_ALDERLAKE_S3
+#endif // D3COLD_SUPPORT
}
Method (_PR3)
{
-#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -285,7 +285,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // SOC_INTEL_ALDERLAKE_S3
+#endif // D3COLD_SUPPORT
}
/*
diff --git a/src/soc/intel/alderlake/acpi/tcss_xhci.asl b/src/soc/intel/alderlake/acpi/tcss_xhci.asl
index c0dc141530..ddc5a6665d 100644
--- a/src/soc/intel/alderlake/acpi/tcss_xhci.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_xhci.asl
@@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
-#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
Return (0x4)
#else
Return (0x3)
-#endif // SOC_INTEL_ALDERLAKE_S3
+#endif // D3COLD_SUPPORT
}
/*
@@ -43,7 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
*/
Name (SD3C, 0)
-#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
Method (_PR0)
{
Return (Package () { \_SB.PCI0.D3C })
@@ -53,7 +53,7 @@ Method (_PR3)
{
Return (Package () { \_SB.PCI0.D3C })
}
-#endif // SOC_INTEL_ALDERLAKE_S3
+#endif // D3COLD_SUPPORT
/*
* XHCI controller _DSM method
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 788ee51a97..d4b16c0d93 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -206,12 +206,6 @@ config SOC_INTEL_I2C_DEV_MAX
int
default 6
-config SOC_INTEL_TIGERLAKE_S3
- bool
- default n
- help
- Select if using S3 instead of S0ix to disable D3Cold
-
config SOC_INTEL_UART_DEV_MAX
int
default 3
diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl
index be9d306f6e..98337a3e5e 100644
--- a/src/soc/intel/tigerlake/acpi/tcss.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss.asl
@@ -676,7 +676,7 @@ Scope (\_SB.PCI0)
}
}
-#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
Method (TCON, 0)
{
/* Reset IOM D3 cold bit if it is in D3 cold now. */
@@ -787,7 +787,7 @@ Scope (\_SB.PCI0)
STAT = 0
}
}
-#endif // SOC_INTEL_TIGERLAKE_S3
+#endif // D3COLD_SUPPORT
/*
* TCSS xHCI device
diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
index 3c19ef621e..bbb0b6a1ad 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl
@@ -27,11 +27,11 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
Method (_S0W, 0x0)
{
-#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
Return (0x04)
#else
Return (0x03)
-#endif // SOC_INTEL_TIGERLAKE_S3
+#endif // D3COLD_SUPPORT
}
/*
@@ -40,7 +40,7 @@ Method (_S0W, 0x0)
*/
Method (_PR0)
{
-#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -52,12 +52,12 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // SOC_INTEL_TIGERLAKE_S3
+#endif // D3COLD_SUPPORT
}
Method (_PR3)
{
-#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -69,7 +69,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // SOC_INTEL_TIGERLAKE_S3
+#endif // D3COLD_SUPPORT
}
/*
diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
index fda58e70cf..a8e19edcce 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
@@ -247,7 +247,7 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
-#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
Return (0x4)
#else
Return (0x3)
@@ -256,7 +256,7 @@ Method (_S0W, 0x0, NotSerialized)
Method (_PR0)
{
-#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -268,12 +268,12 @@ Method (_PR0)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // SOC_INTEL_TIGERLAKE_S3
+#endif // D3COLD_SUPPORT
}
Method (_PR3)
{
-#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
@@ -285,7 +285,7 @@ Method (_PR3)
} Else {
Return (Package() { \_SB.PCI0.TBT1 })
}
-#endif // SOC_INTEL_TIGERLAKE_S3
+#endif // D3COLD_SUPPORT
}
/*
diff --git a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl
index a3b8c8faf7..ddc5a6665d 100644
--- a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl
@@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
-#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
Return (0x4)
#else
Return (0x3)
-#endif // SOC_INTEL_TIGERLAKE_S3
+#endif // D3COLD_SUPPORT
}
/*
@@ -43,7 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
*/
Name (SD3C, 0)
-#if !CONFIG(SOC_INTEL_TIGERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
Method (_PR0)
{
Return (Package () { \_SB.PCI0.D3C })
@@ -53,7 +53,7 @@ Method (_PR3)
{
Return (Package () { \_SB.PCI0.D3C })
}
-#endif // SOC_INTEL_TIGERLAKE_S3
+#endif // D3COLD_SUPPORT
/*
* XHCI controller _DSM method
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-25 01:30:43 +0000