diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-09-17 11:50:39 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@gmail.com> | 2015-10-11 23:57:53 +0000 |
| commit | f45eb062da5a78425d52732b0a0a988b30457c24 (patch) | |
| tree | bbf55e6866ac925954aee49a2d9b8b2915854de7 /src/soc/intel | |
| parent | b593366e349673cd4ef5b933849f78e6e958d626 (diff) | |
skylake: SPI code cleanup
Move base address into iomap.h. Use PCI symbols instead of SPI specific
symbols. Fix comments.
BRANCH=none
BUG=chrome-os-partner:44827
TEST=Build and run on kunimitsu
Change-Id: Id5d21603150b52fd1b71dd448105938bd6aff1a9
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: http://review.coreboot.org/11826
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/bootblock/cpu.c | 10 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/iomap.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/spi.h | 7 | ||||
| -rw-r--r-- | src/soc/intel/skylake/pch.c | 4 |
4 files changed, 11 insertions, 12 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 6c5ab4fe6d..b29acb75ef 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <cpu/intel/microcode/microcode.c> #include <reset.h> +#include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/spi.h> @@ -78,7 +79,7 @@ static void bootblock_mdelay(int ms) static void set_pch_cpu_strap(u8 flex_ratio) { device_t dev = PCH_DEV_SPI; - uint8_t *spibar = (void *)TEMP_SPI_BAR; + uint8_t *spibar = (void *)SPI_BASE_ADDRESS; u32 ssl, ssms, soft_reset_data; u8 pcireg; @@ -89,14 +90,15 @@ static void set_pch_cpu_strap(u8 flex_ratio) pci_write_config8(dev, PCI_COMMAND, pcireg); /* Program Temporary BAR for SPI */ - pci_write_config32(dev, PCH_SPI_BASE_ADDRESS, TEMP_SPI_BAR); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, + SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY); /* Enable Bus Master and MMIO Space */ pcireg = pci_read_config8(dev, PCI_COMMAND); pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config8(dev, PCI_COMMAND, pcireg); - /* Set Strap Lock Disable*/ + /* Set Strap Lock Disable */ ssl = read32(spibar + SPIBAR_RESET_LOCK); ssl |= SPIBAR_RESET_LOCK_DISABLE; write32(spibar + SPIBAR_RESET_LOCK, ssl); @@ -114,7 +116,7 @@ static void set_pch_cpu_strap(u8 flex_ratio) ssms |= SPIBAR_RESET_CTRL_SSMC; write32(spibar + SPIBAR_RESET_CTRL, ssms); - /* Set Strap Lock Enable*/ + /* Set Strap Lock Enable */ ssl = read32(spibar + SPIBAR_RESET_LOCK); ssl |= SPIBAR_RESET_LOCK_ENABLE; write32(spibar + SPIBAR_RESET_LOCK, ssl); diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 333906b348..7dea6ae011 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -53,6 +53,8 @@ #define PCH_PWRM_BASE_ADDRESS 0xfe000000 #define PCH_PWRM_BASE_SIZE 0x10000 +#define SPI_BASE_ADDRESS 0xfe010000 + #define GPIO_BASE_SIZE 0x10000 /* diff --git a/src/soc/intel/skylake/include/soc/spi.h b/src/soc/intel/skylake/include/soc/spi.h index a31c9b2ceb..cf55e9de05 100644 --- a/src/soc/intel/skylake/include/soc/spi.h +++ b/src/soc/intel/skylake/include/soc/spi.h @@ -26,12 +26,7 @@ * should support most common flash chips. */ #define SPIDVID_OFFSET 0x0 -/* Temporay SPI BASE ADDRESS */ -#define TEMP_SPI_BAR 0xFE010000 -/* SPI BASE ADDRESS Register */ -#define B_PCH_SPI_BAR0_MASK 0x0FFF -#define PCH_SPI_BASE_ADDRESS 0x10 -#define SPIBAR_MEMBAR_MASK 0xFFFFF000 + /* Reigsters within the SPIBAR */ #define SPIBAR_SSFC 0xA1 diff --git a/src/soc/intel/skylake/pch.c b/src/soc/intel/skylake/pch.c index 8657402ab8..beaa7bc8a7 100644 --- a/src/soc/intel/skylake/pch.c +++ b/src/soc/intel/skylake/pch.c @@ -45,11 +45,11 @@ void *get_spi_bar(void) device_t dev = PCH_DEV_SPI; uint32_t bar; - bar = pci_read_config32(dev, PCH_SPI_BASE_ADDRESS); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); /* Bits 31-12 are the base address as per EDS for SPI 1F/5, * Don't care about 0-11 bit */ - return (void *)(bar & ~(B_PCH_SPI_BAR0_MASK)); + return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); } u32 pch_read_soft_strap(int id) |