diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-12-28 16:06:45 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-01-08 15:31:19 +0000 |
| commit | ee2e936f4059d8aad4161d44915a05271df1aaae (patch) | |
| tree | 0fcd03d80896097227eb0af35c6144b789b6165c /src/soc/intel | |
| parent | 6267f5dd11aa43fd0bd84f84192db4ddaffa8575 (diff) | |
arch/x86: Unify bootblock MMX register usage
Have same usage of registers with romcc bootblock
and C_ENVIRONMENT_BOOTBLOCK.
Change-Id: Ibfa80e40f0b736a904abf4245fc23efc0cdc458d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/baytrail/romstage/cache_as_ram.inc | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index 945b56d160..8602237d28 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -36,9 +36,6 @@ #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e - /* Save the BIST result. */ - movl %eax, %ebp - cache_as_ram: post_code(0x20) @@ -183,14 +180,13 @@ addrsize_set_high: movl %eax, %esp /* Push the initial TSC value from boot block. The low 32 bits are - * in mm0, and the high 32 bits are in mm1. */ - movd %mm1, %eax + * in mm1, and the high 32 bits are in mm2. */ + movd %mm2, %eax pushl %eax - movd %mm0, %eax + movd %mm1, %eax pushl %eax /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp + movd %mm0, %eax pushl %eax before_romstage: |