diff options
| author | Nico Huber <nico.huber@secunet.com> | 2021-07-26 14:24:53 +0000 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2021-08-04 15:15:39 +0000 |
| commit | e4bc55b843ae3df52c6e92181ac3e9f2e6a949e7 (patch) | |
| tree | ad0bf134b10262bc557a0f5c7dd018581c38b4a1 /src/soc/intel | |
| parent | 6ac8a9f826072b72b064e5885bb8cda65c92a7bb (diff) | |
soc/intel/cannonlake: Disable `TccOffsetClamp` if no offset is given
Change-Id: I4f9b62fd944d8a91d53bc584c88797f23de1e5ca
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 0924763523..4a88458b70 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -611,6 +611,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Set TccActivationOffset */ tconfig->TccActivationOffset = config->tcc_offset; + tconfig->TccOffsetClamp = config->tcc_offset > 0; /* Unlock all GPIO pads */ tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads; |