diff options
| author | Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> | 2022-06-23 22:14:28 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-30 14:07:17 +0000 |
| commit | ddd66ed204f47850d3f3a607344ec5f20a15528a (patch) | |
| tree | b2db8501835712695d552724b95a7f7a3afc24fb /src/soc/intel | |
| parent | 29f8d42d2b054d0d05db40b254ffcbc2f0a4a9df (diff) | |
common/block/cse: Add Kconfigs to indicate when CSE FW sync is performed
CSE FW sync is currently performed in romstage, when uncompressed ME_RW
blobs are used. When compressed blobs are used, this has to be done in
post-RAM stages. Add Kconfigs to describe when the CSE FW sync will be
performed, in romstage or in ramstage.
BRANCH=firmware-brya-14505.B
Change-Id: Iac37aaa5ede5e1cd2d76a58ce2db9cb5b8f42398
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65366
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/cse/Kconfig | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 9621e9ad5f..55a2b49194 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -173,6 +173,20 @@ config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY Mainboard user to select this Kconfig in order to capture pre-cpu reset boot performance telemetry data. +config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE + bool + default y + depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW + help + Use default flow of CSE FW Update in romstage when uncompressed ME_RW blobs are used. + +config SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE + bool + default n + depends on SOC_INTEL_CSE_LITE_COMPRESS_ME_RW + help + Use this option for CSE FW Update when compressed blobs are used. + if STITCH_ME_BIN config CSE_COMPONENTS_PATH |