mainboards: Drop PWRS from GNVS

Initialize variable to 1 to indicate AC power supply.
If platform has EC it will set this correctly based on
whether plugged on the charger or not.

Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

15 files changed, 15 insertions, 15 deletions

diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index b79a446297..225e9db7ea 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -12,7 +12,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	,	8,      // 0x00 - Processor Count
 	PPCM,	8,      // 0x01 - Max PPC State
 	LIDS,	8,      // 0x02 - LID State
-	PWRS,	8,      // 0x03 - AC Power State
+	,	8,      // 0x03 - AC Power State
 	DPTE,	8,      // 0x04 - Enable DPTF
 	CBMC,	32,     // 0x05 - 0x08 - coreboot Memory Console
 	PM1I,	64,     // 0x09 - 0x10 - System Wake Source - PM1 Index
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index 1f2b8ad4f7..aa909a80a7 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -16,7 +16,7 @@ struct __packed global_nvs {
 	uint8_t		unused_was_pcnt; /* 0x00 - Processor Count */
 	uint8_t		ppcm; /* 0x01 - Max PPC State */
 	uint8_t		lids; /* 0x02 - LID State */
-	uint8_t		pwrs; /* 0x03 - AC Power State */
+	uint8_t		unused_was_pwrs; /* 0x03 - AC Power State */
 	uint8_t		dpte; /* 0x04 - Enable DPTF */
 	uint32_t	cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
 	uint64_t	pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index c73b7a7b3f..20b7ed4897 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PRM5,	 8,	/* 0x0a - Lock function parameter */
 	P80D,	32,	/* 0x0b - Debug port (IO 0x80) value */
 	LIDS,	 8,	/* 0x0f - LID state (open = 1) */
-	PWRS,	 8,	/* 0x10 - Power State (AC = 1) */
+	,	 8,	/* 0x10 - Power State (AC = 1) */
 	,	 8,	/* 0x11 - Processor count */
 	TPMP,	 8,	/* 0x12 - TPM Present and Enabled */
 	TLVL,	 8,	/* 0x13 - Throttle Level */
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index a068d1edd4..d6136de170 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -19,7 +19,7 @@ struct __packed global_nvs {
 	u8	prm5; /* 0x0a - Lock function parameter */
 	u32	p80d; /* 0x0b - Debug port (IO 0x80) value */
 	u8	lids; /* 0x0f - LID state (open = 1) */
-	u8	pwrs; /* 0x10 - Power state (AC = 1) */
+	u8	unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
 	u8	unused_was_pcnt; /* 0x11 - Processor Count */
 	u8	tpmp; /* 0x12 - TPM Present and Enabled */
 	u8	tlvl; /* 0x13 - Throttle Level */
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index 9a436710aa..d13e4a4c88 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PRM5,	 8,	/* 0x0a - Lock function parameter */
 	P80D,	32,	/* 0x0b - Debug port (IO 0x80) value */
 	LIDS,	 8,	/* 0x0f - LID state (open = 1) */
-	PWRS,	 8,	/* 0x10 - Power State (AC = 1) */
+	,	 8,	/* 0x10 - Power State (AC = 1) */
 	,	 8,	/* 0x11 - Processor count */
 	TPMP,	 8,	/* 0x12 - TPM Present and Enabled */
 	TLVL,	 8,	/* 0x13 - Throttle Level */
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 7d27c3f822..82ed4f5ad3 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -19,7 +19,7 @@ struct __packed global_nvs {
 	u8	prm5; /* 0x0a - Lock function parameter */
 	u32	p80d; /* 0x0b - Debug port (IO 0x80) value */
 	u8	lids; /* 0x0f - LID state (open = 1) */
-	u8	pwrs; /* 0x10 - Power state (AC = 1) */
+	u8	unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
 	u8      unused_was_pcnt; /* 0x11 - Processor Count */
 	u8	tpmp; /* 0x12 - TPM Present and Enabled */
 	u8	tlvl; /* 0x13 - Throttle Level */
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 70f26e8ef1..1f9ae04493 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -29,7 +29,7 @@ struct __packed global_nvs {
 	u8	s3u0; /* 0x14 - Enable USB in S3 */
 	u8	s33g; /* 0x15 - Enable 3G in S3 */
 	u8	lids; /* 0x16 - LID State */
-	u8	pwrs; /* 0x17 - AC Power State */
+	u8	unused_was_pwrs; /* 0x17 - AC Power State */
 	u32	obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */
 	u32	cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
 	u64	pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
index 8a6bf8787e..876ac89d57 100644
--- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
@@ -29,7 +29,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	S3U0,	8,	// 0x14 - Enable USB in S3
 	S33G,	8,	// 0x15 - Enable 3G in S3
 	LIDS,	8,	// 0x16 - LID State
-	PWRS,	8,	// 0x17 - AC Power State
+	,	8,	// 0x17 - AC Power State
 	,	32,	// 0x18 - 0x1b - CBMEM TOC
 	CBMC,	32,	// 0x1c - 0x1f - coreboot Memory Console
 	PM1I,	64,	// 0x20 - 0x27 - PM1 wake status bit
diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
index d9ecfb3d84..1290fb0ec2 100644
--- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
@@ -13,7 +13,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PPCM,	8,	// 0x04 - Max PPC State
 	TLVL,	8,	// 0x05 - Throttle Level Limit
 	LIDS,	8,	// 0x06 - LID State
-	PWRS,	8,	// 0x07 - AC Power State
+	,	8,	// 0x07 - AC Power State
 	CBMC,	32,	// 0x08 - 0x0b AC Power State
 	PM1I,	64,	// 0x0c - 0x13 PM1 wake status bit
 	GPEI,	64,	// 0x14 - 0x17 GPE wake status bit
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
index cba60f6040..1bbd4c1660 100644
--- a/src/soc/intel/common/block/include/intelblocks/nvs.h
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -13,7 +13,7 @@ struct __packed global_nvs {
 	u8	ppcm; /* 0x04 - Max PPC State */
 	u8	tlvl; /* 0x05 - Throttle Level Limit */
 	u8	lids; /* 0x06 - LID State */
-	u8	pwrs; /* 0x07 - AC Power State */
+	u8	unused_was_pwrs; /* 0x07 - AC Power State */
 	u32	cbmc; /* 0x08 - 0xb coreboot Memory Console */
 	u64	pm1i; /* 0x0c - 0x13 PM1 wake status bit */
 	u64	gpei; /* 0x14 - 0x1b GPE wake status bit */
diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl
index 103397cb4d..5bf706df7d 100644
--- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl
+++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl
@@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PRM5,	 8,	// 0x0a - Lock function parameter
 	P80D,	32,	// 0x0b - Debug port (IO 0x80) value
 	LIDS,	 8,	// 0x0f - LID state (open = 1)
-	PWRS,	 8,	// 0x10 - Power State (AC = 1)
+	,	 8,	// 0x10 - Power State (AC = 1)
 	,	 8,	// 0x11 - Processor count
 	TPMP,	 8,	// 0x12 - TPM Present and Enabled
 	TLVL,	 8,	// 0x13 - Throttle Level
diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h
index 3dd747dbbd..21915576ca 100644
--- a/src/soc/intel/denverton_ns/include/soc/nvs.h
+++ b/src/soc/intel/denverton_ns/include/soc/nvs.h
@@ -17,7 +17,7 @@ struct __packed global_nvs {
 	u8 prm5;  /* 0x0a - Lock function parameter */
 	u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
 	u8 lids;  /* 0x0f - LID state (open = 1) */
-	u8 pwrs;  /* 0x10 - Power state (AC = 1) */
+	u8 unused_was_pwrs;  /* 0x10 - Power state (AC = 1) */
 	u8 unused_was_pcnt;  /* 0x11 - Processor Count */
 	u8 tpmp;  /* 0x12 - TPM Present and Enabled */
 	u8 tlvl;  /* 0x13 - Throttle Level */
diff --git a/src/soc/intel/quark/include/soc/nvs.h b/src/soc/intel/quark/include/soc/nvs.h
index 64378cce3d..9974d5b5e5 100644
--- a/src/soc/intel/quark/include/soc/nvs.h
+++ b/src/soc/intel/quark/include/soc/nvs.h
@@ -7,7 +7,7 @@
 
 struct __packed global_nvs {
 	uint32_t	cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
-	uint8_t		pwrs; /* 0x4 - Power state (AC = 1) */
+	uint8_t		unused_was_pwrs; /* 0x4 - Power state (AC = 1) */
 
 	/* Required for future unified acpi_save_wake_source. */
 	uint32_t	pm1i;
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index 97a69d596d..1bb27ebd8a 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -29,7 +29,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	S3U0,	8,	// 0x14 - Enable USB in S3
 	S33G,	8,	// 0x15 - Enable 3G in S3
 	LIDS,	8,	// 0x16 - LID State
-	PWRS,	8,	// 0x17 - AC Power State
+	,	8,	// 0x17 - AC Power State
 	,	32,	// 0x18 - 0x1b - CBMEM TOC
 	CBMC,	32,	// 0x1c - 0x1f - coreboot Memory Console
 	PM1I,	64,	// 0x20 - 0x27 - PM1 wake status bit
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 21415189c5..e04364a527 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -29,7 +29,7 @@ struct __packed global_nvs {
 	u8	s3u0; /* 0x14 - Enable USB in S3 */
 	u8	s33g; /* 0x15 - Enable 3G in S3 */
 	u8	lids; /* 0x16 - LID State */
-	u8	pwrs; /* 0x17 - AC Power State */
+	u8	unused_was_pwrs; /* 0x17 - AC Power State */
 	u32	obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */
 	u32	cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
 	u64	pm1i; /* 0x20 - 0x27 - PM1 wake status bit */